mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
208 lines
7.0 KiB
Systemverilog
208 lines
7.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module bus_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic mgmt_valid,
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output logic [31:0] mgmt_addr,
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output logic [ 3:0] mgmt_wstrb,
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output logic mgmt_ready,
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output logic user_cmd_valid,
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output logic user_cmd_ready,
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output logic [31:0] user_cmd_addr,
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output logic user_cmd_write,
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output logic [ 1:0] user_cmd_len,
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output logic dma_cmd_valid,
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output logic dma_cmd_ready,
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output logic [31:0] dma_cmd_addr,
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output logic dma_cmd_write,
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output logic [ 1:0] dma_cmd_len,
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output logic rib_cmd_valid,
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output logic [ 1:0] rib_cmd_len,
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output logic apb_valid,
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output logic fault_valid,
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output logic fault_access,
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output logic arb_locked,
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output logic [ 1:0] arb_owner,
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output logic cmd_accepted,
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output logic terminal_rsp
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);
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ribp_if mgmt_ribp ();
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rib_if user_rib ();
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rib_if dma_rib ();
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rib_if rib ();
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ribp_if apb_ribp ();
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(* anyseq *)logic f_mgmt_valid;
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(* anyseq *)logic [31:0] f_mgmt_addr;
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(* anyseq *)logic [31:0] f_mgmt_wdata;
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(* anyseq *)logic [ 3:0] f_mgmt_wstrb;
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(* anyseq *)logic f_user_cmd_valid;
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(* anyseq *)logic [31:0] f_user_cmd_addr;
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(* anyseq *)logic f_user_cmd_write;
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(* anyseq *)logic [ 1:0] f_user_cmd_len;
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(* anyseq *)logic f_user_w_valid;
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(* anyseq *)logic [31:0] f_user_wdata;
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(* anyseq *)logic [ 3:0] f_user_wstrb;
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(* anyseq *)logic f_user_wlast;
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(* anyseq *)logic f_user_rsp_ready;
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(* anyseq *)logic f_dma_cmd_valid;
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(* anyseq *)logic [31:0] f_dma_cmd_addr;
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(* anyseq *)logic f_dma_cmd_write;
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(* anyseq *)logic [ 1:0] f_dma_cmd_len;
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(* anyseq *)logic f_dma_w_valid;
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(* anyseq *)logic [31:0] f_dma_wdata;
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(* anyseq *)logic [ 3:0] f_dma_wstrb;
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(* anyseq *)logic f_dma_wlast;
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(* anyseq *)logic f_dma_rsp_ready;
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logic target_active_q;
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logic target_write_q;
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logic target_write_done_q;
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logic [ 1:0] target_len_q;
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logic [ 1:0] target_beat_q;
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logic [31:0] fault_addr;
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logic [ 3:0] fault_wstrb;
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logic fault_reserved;
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logic [ 1:0] fault_master;
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logic [ 2:0] fault_code;
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logic user_idle;
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assign mgmt_ribp.valid = f_mgmt_valid;
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assign mgmt_ribp.addr = f_mgmt_addr;
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assign mgmt_ribp.wdata = f_mgmt_wdata;
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assign mgmt_ribp.wstrb = f_mgmt_wstrb;
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assign user_rib.cmd_valid = f_user_cmd_valid;
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assign user_rib.cmd_addr = f_user_cmd_addr;
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assign user_rib.cmd_write = f_user_cmd_write;
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assign user_rib.cmd_len = f_user_cmd_len;
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assign user_rib.w_valid = f_user_w_valid;
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assign user_rib.wdata = f_user_wdata;
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assign user_rib.wstrb = f_user_wstrb;
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assign user_rib.wlast = f_user_wlast;
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assign user_rib.rsp_ready = f_user_rsp_ready;
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assign dma_rib.cmd_valid = f_dma_cmd_valid;
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assign dma_rib.cmd_addr = f_dma_cmd_addr;
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assign dma_rib.cmd_write = f_dma_cmd_write;
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assign dma_rib.cmd_len = f_dma_cmd_len;
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assign dma_rib.w_valid = f_dma_w_valid;
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assign dma_rib.wdata = f_dma_wdata;
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assign dma_rib.wstrb = f_dma_wstrb;
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assign dma_rib.wlast = f_dma_wlast;
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assign dma_rib.rsp_ready = f_dma_rsp_ready;
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assign rib.cmd_ready = ~target_active_q;
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assign rib.w_ready = target_active_q && target_write_q && ~target_write_done_q;
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assign rib.rsp_valid = target_active_q && (~target_write_q || target_write_done_q);
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assign rib.rdata = 32'hCAFE_0000 | {30'd0, target_beat_q};
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assign rib.resp_err = 1'b0;
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assign rib.resp_code = `RIB_RESP_OK;
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assign rib.rsp_beat = target_beat_q;
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assign rib.rsp_last = target_write_q || (target_beat_q == target_len_q);
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always_ff @(posedge clk_i) begin
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if (!rst_n_i) begin
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target_active_q <= 1'b0;
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target_write_q <= 1'b0;
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target_write_done_q <= 1'b0;
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target_len_q <= '0;
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target_beat_q <= '0;
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end else begin
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if (rib.cmd_valid && rib.cmd_ready) begin
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target_active_q <= 1'b1;
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target_write_q <= rib.cmd_write;
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target_write_done_q <= 1'b0;
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target_len_q <= rib.cmd_len;
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target_beat_q <= '0;
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end
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if (rib.w_valid && rib.w_ready) begin
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if (rib.wlast) begin
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target_write_done_q <= 1'b1;
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target_beat_q <= target_len_q;
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end else begin
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target_beat_q <= target_beat_q + 1'b1;
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end
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end
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if (rib.rsp_valid && rib.rsp_ready) begin
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if (rib.rsp_last) begin
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target_active_q <= 1'b0;
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end else begin
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target_beat_q <= target_beat_q + 1'b1;
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end
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end
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end
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end
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assign apb_ribp.ready = apb_ribp.valid;
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assign apb_ribp.rdata = 32'h1234_5678;
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assign apb_ribp.resp_err = 1'b0;
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assign mgmt_valid = mgmt_ribp.valid;
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assign mgmt_addr = mgmt_ribp.addr;
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assign mgmt_wstrb = mgmt_ribp.wstrb;
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assign mgmt_ready = mgmt_ribp.ready;
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assign user_cmd_valid = user_rib.cmd_valid;
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assign user_cmd_ready = user_rib.cmd_ready;
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assign user_cmd_addr = user_rib.cmd_addr;
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assign user_cmd_write = user_rib.cmd_write;
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assign user_cmd_len = user_rib.cmd_len;
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assign dma_cmd_valid = dma_rib.cmd_valid;
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assign dma_cmd_ready = dma_rib.cmd_ready;
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assign dma_cmd_addr = dma_rib.cmd_addr;
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assign dma_cmd_write = dma_rib.cmd_write;
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assign dma_cmd_len = dma_rib.cmd_len;
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assign rib_cmd_valid = rib.cmd_valid;
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assign rib_cmd_len = rib.cmd_len;
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assign apb_valid = apb_ribp.valid;
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bus u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.mgmt_ribp (mgmt_ribp),
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.user_rib (user_rib),
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.dma_rib (dma_rib),
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.user_bus_enable_i(1'b1),
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.user_bus_idle_o (user_idle),
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.rib (rib),
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.apb_ribp (apb_ribp),
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.perf_enable_i (1'b0),
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.perf_clear_i (1'b0),
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.fault_valid_o (fault_valid),
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.fault_addr_o (fault_addr),
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.fault_wstrb_o (fault_wstrb),
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.fault_reserved_o (fault_reserved),
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.fault_access_o (fault_access),
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.fault_master_o (fault_master),
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.fault_code_o (fault_code),
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.perf_mgmt_wait_o (),
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.perf_user_wait_o (),
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.perf_dma_wait_o (),
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.perf_ribp_wait_o (),
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.perf_apb_wait_o (),
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.perf_sdram_wait_o(),
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.perf_psram_wait_o(),
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.perf_flash_wait_o()
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);
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assign arb_locked = u_dut.s_mstr_lock_q;
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assign arb_owner = u_dut.s_mstr_id_q;
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assign cmd_accepted = u_dut.s_cmd_accepted_q;
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assign terminal_rsp = u_dut.s_terminal_rsp;
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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