mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
132 lines
5.1 KiB
Systemverilog
132 lines
5.1 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module sysctrl_formal_design (
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic rib_valid,
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output logic [31:0] rib_addr,
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output logic [31:0] rib_wdata,
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output logic [ 3:0] rib_wstrb,
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output logic rib_ready,
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output logic [ 7:0] ip_sel,
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output logic [ 4:0] core_sel,
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output logic [ 5:0] user_reset,
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output logic user_bus_enable,
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output logic user_config_error,
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output logic [ 2:0] pll_cfg,
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output logic pll_req_valid,
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output logic pll_req_ready,
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output logic pll_busy,
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output logic pll_error,
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output logic [ 1:0] pll_error_reason,
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output logic pll_rsp_valid,
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output logic fault_valid,
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output logic [31:0] fault_addr,
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output logic [ 3:0] fault_wstrb,
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output logic fault_reserved,
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output logic fault_pending,
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output logic fault_write,
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output logic [ 2:0] fault_reason,
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output logic [31:0] fault_addr_q,
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output logic [31:0] fault_count
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);
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ribp_if rib ();
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sysctrl_if sysctrl ();
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pll_ctrl_if pll_ctrl ();
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(* anyseq *)logic f_rib_valid;
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(* anyseq *)logic [31:0] f_rib_addr;
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(* anyseq *)logic [31:0] f_rib_wdata;
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(* anyseq *)logic [ 3:0] f_rib_wstrb;
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(* anyseq *)logic f_pll_req_ready;
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(* anyseq *)logic [ 2:0] f_pll_active_sel;
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(* anyseq *)logic f_pll_active_valid;
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(* anyseq *)logic f_pll_safe_clk;
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(* anyseq *)logic f_pll_lock;
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(* anyseq *)logic [ 1:0] f_pll_rsp_error;
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(* anyseq *)logic f_pll_rsp_valid;
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(* anyseq *)logic f_pll_capable;
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(* anyseq *)logic f_fault_valid;
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(* anyseq *)logic [31:0] f_fault_addr;
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(* anyseq *)logic [ 3:0] f_fault_wstrb;
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(* anyseq *)logic f_fault_reserved;
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assign rib.valid = f_rib_valid;
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assign rib.addr = f_rib_addr;
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assign rib.wdata = f_rib_wdata;
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assign rib.wstrb = f_rib_wstrb;
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assign sysctrl.user_bus_idle_i = 1'b1;
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assign sysctrl.fault_access_i = 1'b0;
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assign sysctrl.fault_master_i = '0;
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assign sysctrl.fault_code_i = f_fault_reserved ? `RIB_RESP_RESERVED : `RIB_RESP_DECERR;
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assign sysctrl.perf_mgmt_wait_i = '0;
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assign sysctrl.perf_user_wait_i = '0;
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assign sysctrl.perf_dma_wait_i = '0;
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assign sysctrl.perf_ribp_wait_i = '0;
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assign sysctrl.perf_apb_wait_i = '0;
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assign sysctrl.perf_sdram_wait_i = '0;
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assign sysctrl.perf_psram_wait_i = '0;
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assign sysctrl.perf_flash_wait_i = '0;
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assign pll_ctrl.req_ready_i = f_pll_req_ready;
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assign pll_ctrl.rsp_active_sel_i = f_pll_active_sel;
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assign pll_ctrl.rsp_active_valid_i = f_pll_active_valid;
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assign pll_ctrl.rsp_safe_clk_i = f_pll_safe_clk;
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assign pll_ctrl.rsp_pll_lock_i = f_pll_lock;
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assign pll_ctrl.rsp_error_i = f_pll_rsp_error;
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assign pll_ctrl.rsp_valid_i = f_pll_rsp_valid;
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assign pll_ctrl.capable_i = f_pll_capable;
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assign rib_valid = rib.valid;
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assign rib_addr = rib.addr;
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assign rib_wdata = rib.wdata;
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assign rib_wstrb = rib.wstrb;
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assign rib_ready = rib.ready;
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assign ip_sel = sysctrl.ip_sel_o;
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assign core_sel = u_dut.s_sysctrl_coresel_q;
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assign user_reset = u_dut.s_user_reset_q;
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assign user_bus_enable = u_dut.s_user_running_q;
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assign user_config_error = u_dut.s_user_config_error_q;
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assign pll_cfg = u_dut.s_pll_cfg_q;
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assign pll_req_valid = pll_ctrl.req_valid_o;
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assign pll_req_ready = pll_ctrl.req_ready_i;
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assign pll_busy = u_dut.s_pll_busy_q;
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assign pll_error = u_dut.s_pll_error_q;
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assign pll_error_reason = u_dut.s_pll_error_reason_q;
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assign pll_rsp_valid = pll_ctrl.rsp_valid_i;
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assign fault_valid = f_fault_valid;
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assign fault_addr = f_fault_addr;
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assign fault_wstrb = f_fault_wstrb;
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assign fault_reserved = f_fault_reserved;
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assign fault_pending = u_dut.s_fault_pending_q;
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assign fault_write = u_dut.s_fault_write_q;
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assign fault_reason = u_dut.s_fault_reason_q;
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assign fault_addr_q = u_dut.s_fault_addr_q;
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assign fault_count = u_dut.s_fault_count_q;
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ribp_sysctrl u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (f_fault_valid),
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.fault_addr_i (f_fault_addr),
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.fault_wstrb_i (f_fault_wstrb),
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.fault_reserved_i(f_fault_reserved),
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.ribp (rib),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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