mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
28 lines
887 B
Systemverilog
28 lines
887 B
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module core_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic [31:0] irq_i,
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ribp_if.master ribp
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// verilog_format: on
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);
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mgmt_core_wrapper u_mgmt_core_wrapper (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.irq_i (irq_i),
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.ribp (ribp)
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);
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endmodule
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