mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
192 lines
7.1 KiB
Systemverilog
192 lines
7.1 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "user_extensions.svh"
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`include "soc_irq_config.svh"
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module retrosoc (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic clkdiv4_i,
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pll_ctrl_if.sysctrl pll_ctrl,
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`ifdef HAVE_SRAM_IF
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ram_if.master ram,
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`endif
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gpio_if.soc_pad gpio,
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uart_if.dut uart0,
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xpi_if.dut xpi,
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sdram_if.dut sdram
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// verilog_format: on
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);
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// verilog_format: off
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// Generated fabric links reuse the common ribp_if contract.
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`include "soc_fabric_interfaces.svh"
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user_gpio_if u_user_gpio_if ();
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// ip interface
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gpio_if u_gpio_if ();
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psram_if u_psram_if ();
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spi_if u_spisd_if ();
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i2c_if u_i2c0_if ();
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i2s_if u_i2s_if ();
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onewire_if u_onewire_if ();
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sysctrl_if u_sysctrl_if ();
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dvp_if u_dvp_if ();
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sdio_if u_sdio_if ();
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opipsram_if u_opipsram_if ();
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i2c_if u_i2c1_if ();
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uart_if u_uart1_if ();
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pwm_if u_pwm_if ();
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ps2_if u_ps2_if ();
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// verilog_format: on
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logic s_tmr_capch;
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logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
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logic [ `SOC_IRQ_RIBP_WIDTH-1:0] s_ribp_irq;
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logic [ `SOC_IRQ_APB_WIDTH-1:0] s_apb_irq;
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logic s_bus_fault_valid;
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logic [ 31:0] s_bus_fault_addr;
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logic [ 3:0] s_bus_fault_wstrb;
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logic s_bus_fault_reserved;
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logic s_bus_fault_access;
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logic [ 1:0] s_bus_fault_master;
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logic [ 2:0] s_bus_fault_code;
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logic s_perf_enable;
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logic s_perf_clear;
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logic [ 63:0] s_perf_mgmt_wait;
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logic [ 63:0] s_perf_user_wait;
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logic [ 63:0] s_perf_dma_wait;
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logic [ 63:0] s_perf_ribp_wait;
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logic [ 63:0] s_perf_apb_wait;
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logic [ 63:0] s_perf_sdram_wait;
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logic [ 63:0] s_perf_psram_wait;
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logic [ 63:0] s_perf_flash_wait;
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logic [`SOC_IRQ_VECTOR_WIDTH-1:0] s_user_irq;
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assign u_sysctrl_if.fault_access_i = s_bus_fault_access;
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assign u_sysctrl_if.fault_master_i = s_bus_fault_master;
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assign u_sysctrl_if.fault_code_i = s_bus_fault_code;
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assign s_perf_enable = u_sysctrl_if.perf_enable_o;
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assign s_perf_clear = u_sysctrl_if.perf_clear_o;
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assign u_sysctrl_if.perf_mgmt_wait_i = s_perf_mgmt_wait;
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assign u_sysctrl_if.perf_user_wait_i = s_perf_user_wait;
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assign u_sysctrl_if.perf_dma_wait_i = s_perf_dma_wait;
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assign u_sysctrl_if.perf_ribp_wait_i = s_perf_ribp_wait;
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assign u_sysctrl_if.perf_apb_wait_i = s_perf_apb_wait;
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assign u_sysctrl_if.perf_sdram_wait_i = s_perf_sdram_wait;
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assign u_sysctrl_if.perf_psram_wait_i = s_perf_psram_wait;
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assign u_sysctrl_if.perf_flash_wait_i = s_perf_flash_wait;
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gpio_pad_bridge u_gpio_pad_bridge (
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.inner(u_gpio_if),
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.outer(gpio)
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);
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// Generated IRQ vector wiring defaults all unallocated core IRQ bits low.
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`include "soc_irq_wiring.svh"
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// Generated GPIO alternate-function wiring is checked against soc_topology.json.
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`include "soc_gpio_alt_bindings.svh"
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core_wrapper u_core_wrapper (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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`include "soc_mgmt_core_wrapper_fabric.svh"
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.irq_i (s_irq)
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);
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assign s_user_irq = u_sysctrl_if.user_bus_enable_o ? s_irq : '0;
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user_core_top u_user_core_top (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.irq_i (s_user_irq),
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.sel_i (u_sysctrl_if.core_sel_o),
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`include "soc_user_core_fabric.svh"
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.core_reset_i(u_sysctrl_if.core_reset_o)
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);
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bus u_bus (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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`ifdef HAVE_SRAM_IF
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.ram (ram),
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`endif
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.user_bus_enable_i(u_sysctrl_if.user_bus_enable_o),
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.user_bus_idle_o (u_sysctrl_if.user_bus_idle_i),
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`include "soc_bus_fabric.svh"
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.perf_enable_i (s_perf_enable),
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.perf_clear_i (s_perf_clear),
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.fault_valid_o (s_bus_fault_valid),
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.fault_addr_o (s_bus_fault_addr),
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.fault_wstrb_o (s_bus_fault_wstrb),
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.fault_reserved_o (s_bus_fault_reserved),
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.fault_access_o (s_bus_fault_access),
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.fault_master_o (s_bus_fault_master),
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.fault_code_o (s_bus_fault_code),
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.perf_mgmt_wait_o (s_perf_mgmt_wait),
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.perf_user_wait_o (s_perf_user_wait),
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.perf_dma_wait_o (s_perf_dma_wait),
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.perf_ribp_wait_o (s_perf_ribp_wait),
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.perf_apb_wait_o (s_perf_apb_wait),
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.perf_sdram_wait_o(s_perf_sdram_wait),
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.perf_psram_wait_o(s_perf_psram_wait),
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.perf_flash_wait_o(s_perf_flash_wait)
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);
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ip_ribp_wrapper u_ip_ribp_wrapper (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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`include "ip_ribp_wrapper_fabric.svh"
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.gpio (u_gpio_if),
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.user_gpio (u_user_gpio_if),
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.uart (uart0),
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.psram (u_psram_if),
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.spisd (u_spisd_if),
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.i2c0 (u_i2c0_if),
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.i2s (u_i2s_if),
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.onewire (u_onewire_if),
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.xpi (xpi),
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.sysctrl (u_sysctrl_if),
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.pll_ctrl (pll_ctrl),
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.sdram (sdram),
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.dvp (u_dvp_if),
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.sdio (u_sdio_if),
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.opipsram (u_opipsram_if),
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.i2c1 (u_i2c1_if),
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.fault_valid_i (s_bus_fault_valid),
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.fault_addr_i (s_bus_fault_addr),
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.fault_wstrb_i (s_bus_fault_wstrb),
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.fault_reserved_i(s_bus_fault_reserved),
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.irq_o (s_ribp_irq)
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);
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ip_apb_wrapper u_ip_apb_wrapper (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i(rst_aud_n_i),
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.tmr_capch_i(s_tmr_capch),
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`include "soc_ip_apb_wrapper_fabric.svh"
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.uart (u_uart1_if),
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.pwm (u_pwm_if),
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.ps2 (u_ps2_if),
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.ip_sel_i (u_sysctrl_if.ip_sel_o),
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.user_gpio (u_user_gpio_if),
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.irq_o (s_apb_irq)
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);
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endmodule
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