mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
26 lines
872 B
Systemverilog
26 lines
872 B
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef RETROSOC_RIB_DEFS_SVH
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`define RETROSOC_RIB_DEFS_SVH
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`define RIB_RESP_OK 3'd0
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`define RIB_RESP_DECERR 3'd1
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`define RIB_RESP_PROTERR 3'd2
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`define RIB_RESP_SLVERR 3'd3
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`define RIB_RESP_TIMEOUT 3'd4
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`define RIB_RESP_RESERVED 3'd5
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`define RIB_RESP_BURSTERR 3'd6
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`define RIB_LEN_INCR1 2'd0
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`define RIB_LEN_INCR4 2'd3
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`endif
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