mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
81 lines
2.0 KiB
Systemverilog
81 lines
2.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef RETROSOC_RIB_IF_SV
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`define RETROSOC_RIB_IF_SV
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// SoC-owned split-channel RIB contract. Version 1 supports one outstanding
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// 32-bit INCR1 or INCR4 transaction and does not carry transaction IDs.
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interface rib_if ();
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logic cmd_valid;
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logic cmd_ready;
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logic [31:0] cmd_addr;
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logic cmd_write;
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logic [ 1:0] cmd_len;
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logic w_valid;
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logic w_ready;
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logic [31:0] wdata;
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logic [ 3:0] wstrb;
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logic wlast;
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logic rsp_valid;
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logic rsp_ready;
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logic [31:0] rdata;
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logic resp_err;
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logic [ 2:0] resp_code;
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logic [ 1:0] rsp_beat;
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logic rsp_last;
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modport slave(
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input cmd_valid,
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output cmd_ready,
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input cmd_addr,
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input cmd_write,
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input cmd_len,
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input w_valid,
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output w_ready,
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input wdata,
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input wstrb,
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input wlast,
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output rsp_valid,
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input rsp_ready,
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output rdata,
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output resp_err,
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output resp_code,
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output rsp_beat,
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output rsp_last
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);
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modport master(
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output cmd_valid,
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input cmd_ready,
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output cmd_addr,
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output cmd_write,
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output cmd_len,
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output w_valid,
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input w_ready,
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output wdata,
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output wstrb,
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output wlast,
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input rsp_valid,
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output rsp_ready,
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input rdata,
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input resp_err,
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input resp_code,
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input rsp_beat,
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input rsp_last
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);
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endinterface
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`endif
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