mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
a87236ae33
- Renamed and to and respectively across various test files and modules. - Updated response codes in tests to use new definitions (). - Added new testbench to validate RIB to RAM interactions. - Created for testing RIBP topology routing. - Adjusted memory map tests to reflect new interface names. - Ensured all references to old interface names were replaced in Python test scripts. - Verified that all test cases pass with the new interface structure.
114 lines
2.8 KiB
Systemverilog
114 lines
2.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "rib_defs.svh"
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module ribp2rib #(
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parameter bit SYNC_RESET = 1'b0
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) (
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input logic clk_i,
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input logic rst_n_i,
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ribp_if.slave ribp,
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rib_if.master rib
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);
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localparam logic [1:0] FSM_CMD = 2'd0;
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localparam logic [1:0] FSM_WDATA = 2'd1;
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localparam logic [1:0] FSM_RESP = 2'd2;
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logic [1:0] s_fsm_d, s_fsm_q;
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logic [31:0] s_wdata_q;
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logic [ 3:0] s_wstrb_q;
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logic s_cmd_hdshk;
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assign s_cmd_hdshk = rib.cmd_valid && rib.cmd_ready;
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assign rib.cmd_valid = s_fsm_q == FSM_CMD && ribp.valid;
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assign rib.cmd_addr = ribp.addr;
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assign rib.cmd_write = |ribp.wstrb;
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assign rib.cmd_len = `RIB_LEN_INCR1;
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assign rib.w_valid = s_fsm_q == FSM_WDATA;
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assign rib.wdata = s_wdata_q;
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assign rib.wstrb = s_wstrb_q;
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assign rib.wlast = 1'b1;
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assign rib.rsp_ready = s_fsm_q == FSM_RESP;
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assign ribp.ready = s_fsm_q == FSM_RESP && rib.rsp_valid;
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assign ribp.rdata = rib.rdata;
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assign ribp.resp_err = ribp.ready && rib.resp_err;
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always_comb begin
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s_fsm_d = s_fsm_q;
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unique case (s_fsm_q)
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FSM_CMD: begin
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if (s_cmd_hdshk) begin
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s_fsm_d = rib.cmd_write ? FSM_WDATA : FSM_RESP;
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end
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end
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FSM_WDATA: begin
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if (rib.w_valid && rib.w_ready) begin
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s_fsm_d = FSM_RESP;
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end
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end
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FSM_RESP: begin
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if (rib.rsp_valid) begin
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s_fsm_d = FSM_CMD;
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end
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end
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default: s_fsm_d = FSM_CMD;
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endcase
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end
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if (SYNC_RESET) begin : GEN_SYNC_RESET
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dffsr #(2) u_fsm_dffsr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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dffesr #(32) u_wdata_dffesr (
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clk_i,
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rst_n_i,
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s_cmd_hdshk,
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ribp.wdata,
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s_wdata_q
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);
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dffesr #(4) u_wstrb_dffesr (
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clk_i,
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rst_n_i,
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s_cmd_hdshk,
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ribp.wstrb,
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s_wstrb_q
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);
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end else begin : GEN_ASYNC_RESET
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dffr #(2) u_fsm_dffr (
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clk_i,
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rst_n_i,
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s_fsm_d,
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s_fsm_q
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);
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dffer #(32) u_wdata_dffer (
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clk_i,
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rst_n_i,
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s_cmd_hdshk,
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ribp.wdata,
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s_wdata_q
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);
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dffer #(4) u_wstrb_dffer (
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clk_i,
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rst_n_i,
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s_cmd_hdshk,
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ribp.wstrb,
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s_wstrb_q
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);
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end
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endmodule
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