mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
b5b5492659
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if. - Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface. - Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs. - Removed legacy GPIO handling from retrosoc and retrosoc_asic modules. - Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files. - Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py. - Created new makefiles for IP MDD configurations to support the updated GPIO structure. - Updated regression tests to include new configurations and ensure compatibility with the changes.
166 lines
5.2 KiB
Systemverilog
166 lines
5.2 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "uart_define.svh"
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`include "pwm_define.svh"
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`include "ps2_define.svh"
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`include "mdd_config.svh"
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module ip_apb_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic tmr_capch_i,
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nmi_if.slave nmi,
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uart_if.dut uart,
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pwm_if.dut pwm,
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ps2_if.dut ps2,
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`ifdef IP_MDD
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input logic [`USER_IPSEL_WIDTH-1:0] ip_sel_i,
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user_gpio_if.user_ip user_gpio,
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`endif
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output logic [ 6:0] irq_o
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// verilog_format: on
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);
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// verilog_format: off
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apb4_if u_archinfo_apb_if (clk_i, rst_n_i);
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apb4_if u_rng_apb_if (clk_i, rst_n_i);
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apb4_if u_uart1_apb_if (clk_i, rst_n_i);
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apb4_if u_pwm_apb_if (clk_i, rst_n_i);
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apb4_if u_ps2_apb_if (clk_i, rst_n_i);
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apb4_if u_rtc_apb_if (clk_i, rst_n_i);
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apb4_if u_wdg_apb_if (clk_i, rst_n_i);
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apb4_if u_crc_apb_if (clk_i, rst_n_i);
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apb4_if u_tmr_apb_if (clk_i, rst_n_i);
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// NOTE: for FPGA-compatible
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apb4_pure_if u_archinfo_apb_pure_if ();
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apb4_pure_if u_rng_apb_pure_if ();
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apb4_pure_if u_uart1_apb_pure_if ();
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apb4_pure_if u_pwm_apb_pure_if ();
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apb4_pure_if u_ps2_apb_pure_if ();
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apb4_pure_if u_rtc_apb_pure_if ();
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apb4_pure_if u_wdg_apb_pure_if ();
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apb4_pure_if u_crc_apb_pure_if ();
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apb4_pure_if u_tmr_apb_pure_if ();
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// low freq clock perip
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rtc_if u_rtc_if (clk_aud_i, rst_aud_n_i);
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wdg_if u_wdg_if (clk_aud_i);
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tmr_if u_tmr_if (clk_aud_i);
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assign u_tmr_if.capch_i = tmr_capch_i;
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// verilog_format: on
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// verilog_format: off
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`ifdef IP_MDD
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apb4_if u_user_ip_apb_if (clk_i, rst_n_i);
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apb4_pure_if u_user_ip_apb_pure_if ();
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`endif
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// verilog_format: on
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apb4_if_bridge u_archinfo_apb_bridge (
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.apb_pure(u_archinfo_apb_pure_if),
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.timed (u_archinfo_apb_if)
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);
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apb4_if_bridge u_rng_apb_bridge (
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.apb_pure(u_rng_apb_pure_if),
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.timed (u_rng_apb_if)
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);
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apb4_if_bridge u_uart1_apb_bridge (
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.apb_pure(u_uart1_apb_pure_if),
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.timed (u_uart1_apb_if)
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);
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apb4_if_bridge u_pwm_apb_bridge (
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.apb_pure(u_pwm_apb_pure_if),
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.timed (u_pwm_apb_if)
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);
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apb4_if_bridge u_ps2_apb_bridge (
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.apb_pure(u_ps2_apb_pure_if),
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.timed (u_ps2_apb_if)
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);
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apb4_if_bridge u_rtc_apb_bridge (
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.apb_pure(u_rtc_apb_pure_if),
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.timed (u_rtc_apb_if)
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);
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apb4_if_bridge u_wdg_apb_bridge (
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.apb_pure(u_wdg_apb_pure_if),
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.timed (u_wdg_apb_if)
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);
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apb4_if_bridge u_crc_apb_bridge (
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.apb_pure(u_crc_apb_pure_if),
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.timed (u_crc_apb_if)
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);
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apb4_if_bridge u_tmr_apb_bridge (
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.apb_pure(u_tmr_apb_pure_if),
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.timed (u_tmr_apb_if)
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);
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`ifdef IP_MDD
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apb4_if_bridge u_user_ip_apb_bridge (
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.apb_pure(u_user_ip_apb_pure_if),
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.timed (u_user_ip_apb_if)
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);
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`endif
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// verilog_format: off
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apb4_archinfo u_apb4_archinfo (u_archinfo_apb_if);
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apb4_rng u_apb4_rng (u_rng_apb_if);
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apb4_uart #(.FIFO_DEPTH(32)) u_apb4_uart (u_uart1_apb_if, uart);
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apb4_pwm u_apb4_pwm (u_pwm_apb_if, pwm);
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apb4_ps2 u_apb4_ps2 (u_ps2_apb_if, ps2);
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apb4_rtc u_apb4_rtc (u_rtc_apb_if, u_rtc_if);
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apb4_wdg u_apb4_wdg (u_wdg_apb_if, u_wdg_if);
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apb4_crc u_apb4_crc (u_crc_apb_if);
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apb4_tmr u_apb4_tmr (u_tmr_apb_if, u_tmr_if);
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// verilog_format: on
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// handle irq signals
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assign irq_o[0] = uart.irq_o;
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assign irq_o[1] = pwm.irq_o;
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assign irq_o[2] = ps2.irq_o;
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assign irq_o[3] = u_rtc_if.irq_o;
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assign irq_o[4] = u_wdg_if.rst_o;
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assign irq_o[5] = u_tmr_if.irq_o;
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assign irq_o[6] = 1'b0;
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nmi2apb u_nmi2apb (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.nmi (nmi),
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`ifdef IP_MDD
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.user_ip (u_user_ip_apb_pure_if),
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`endif
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.archinfo(u_archinfo_apb_pure_if),
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.rng (u_rng_apb_pure_if),
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.uart (u_uart1_apb_pure_if),
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.pwm (u_pwm_apb_pure_if),
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.ps2 (u_ps2_apb_pure_if),
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.rtc (u_rtc_apb_pure_if),
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.wdg (u_wdg_apb_pure_if),
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.crc (u_crc_apb_pure_if),
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.tmr (u_tmr_apb_pure_if)
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);
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`ifdef IP_MDD
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user_ip_wrapper u_user_ip_wrapper (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.sel_i (ip_sel_i),
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.gpio (user_gpio),
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.apb (u_user_ip_apb_if)
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);
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`endif
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endmodule
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