mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5b5492659
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if. - Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface. - Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs. - Removed legacy GPIO handling from retrosoc and retrosoc_asic modules. - Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files. - Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py. - Created new makefiles for IP MDD configurations to support the updated GPIO structure. - Updated regression tests to include new configurations and ensure compatibility with the changes.
82 lines
3.0 KiB
Systemverilog
82 lines
3.0 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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/* NOTE: README FIRST
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* 0. copy this file as `user_ip_design.sv`
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* 1. create a new folder `userip` and simply put `user_ip_design.sv` into `userip` folder
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* 2. put all user custom design files into `userip` folder
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* - instance top module of user design in `user_ip_design.sv`
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* - create a filelist named `userip.fl` to include all files needed to be included
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* 3. archive 'userip' as `userip.zip` and upload `userip.zip` to cloud platform
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*/
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// NOTE: dont remove `ID` parameter and port defines
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module user_ip_design_template #(
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parameter int ID = 8'd255
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) (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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user_gpio_if.user_ip gpio,
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apb4_if.slave apb
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// verilog_format: on
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);
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// ========== USER CUSTOM AREA ==============
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// NOTE: define constants by using `localparam`
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// and dont DELETE or MODIFY the addr and read
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// logic of `USER_IP_APB_ID`.
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// User should add new register defines like
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// `USER_IP_APB_XX`.
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localparam USER_IP_APB_ID = 8'h00;
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localparam USER_IP_APB_XX = 8'h04;
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// ========== USER CUSTOM AREA END ==========
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// ========== USER CUSTOM AREA ==============
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// NOTE: recommand define variables here
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logic s_apb_wr_hdshk, s_apb_rd_hdshk;
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// ========== USER CUSTOM AREA END ==========
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assign s_apb_wr_hdshk = apb.psel && apb.penable && apb.pwrite;
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assign s_apb_rd_hdshk = apb.psel && apb.penable && (~apb.pwrite);
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// `pready` can be set according to requirements.
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assign apb.pready = 1'b1;
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// error handling is not supported, `pslverr`
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// must be set to 0.
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assign apb.pslverr = 1'b0;
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always_comb begin
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apb.prdata = '0;
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if (s_apb_rd_hdshk) begin
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unique case (apb.paddr[7:0])
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USER_IP_APB_ID: apb.prdata = {24'd0, ID};
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// NOTE: If needed, define the register's read logic here, like
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// `USER_IP_APB_XX: apb.prdata = {xxx}`
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default: apb.prdata = '0;
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endcase
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end
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end
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// ========== USER CUSTOM AREA ==============
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// NOTE: If needed, define io logic here.
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// `oe_o` is active high, meaning GPIO is output when `oe_o[x]` is 1'b1.
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// Pad electrical controls remain owned by the native GPIO controller.
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assign gpio.oe_o = '0;
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assign gpio.do_o = '0;
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// ========== USER CUSTOM AREA END ==========
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// ====== INSTANCE USER CUSTOM TOP DESIGN HERE ======
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// ==================================================
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// ==================================================
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endmodule
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