mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5b5492659
- Updated the GPIO interface in multiple modules to use the new user_gpio_if structure instead of the legacy gpio_if. - Modified the ip_apb_wrapper, ip_nmi_wrapper, user_ip_design_template, user_ip_top, and user_ip_wrapper to reflect the new GPIO interface. - Increased the USER_GPIO_NUM from 16 to 32 in mdd_config.svh to accommodate more GPIOs. - Removed legacy GPIO handling from retrosoc and retrosoc_asic modules. - Implemented a migration script in generate_mpw.py to automatically update legacy GPIO ports in source files. - Added tests for the new GPIO user interface and ensured proper functionality through gpio_user_mux_tb and gpio_user_mux.py. - Created new makefiles for IP MDD configurations to support the updated GPIO structure. - Updated regression tests to include new configurations and ensure compatibility with the changes.
59 lines
2.3 KiB
Systemverilog
59 lines
2.3 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mdd_config.svh"
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module user_ip_wrapper (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic [`USER_IPSEL_WIDTH-1:0] sel_i,
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user_gpio_if.user_ip gpio,
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apb4_if.slave apb
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// verilog_format: on
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);
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// verilog_format: off
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apb4_if u_demo_apb4_if(clk_i, rst_n_i);
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apb4_if u_user_apb4_if(clk_i, rst_n_i);
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apb4_archinfo u_apb4_archinfo_ip(u_demo_apb4_if);
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// verilog_format: on
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assign apb.pready = ~(|sel_i) ? u_demo_apb4_if.pready : u_user_apb4_if.pready;
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assign apb.prdata = ~(|sel_i) ? u_demo_apb4_if.prdata : u_user_apb4_if.prdata;
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assign apb.pslverr = ~(|sel_i) ? u_demo_apb4_if.pslverr : u_user_apb4_if.pslverr;
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assign u_demo_apb4_if.paddr = ~(|sel_i) ? apb.paddr : '0;
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assign u_demo_apb4_if.pprot = ~(|sel_i) ? apb.pprot : '0;
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assign u_demo_apb4_if.psel = ~(|sel_i) ? apb.psel : '0;
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assign u_demo_apb4_if.penable = ~(|sel_i) ? apb.penable : '0;
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assign u_demo_apb4_if.pwrite = ~(|sel_i) ? apb.pwrite : '0;
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assign u_demo_apb4_if.pwdata = ~(|sel_i) ? apb.pwdata : '0;
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assign u_demo_apb4_if.pstrb = ~(|sel_i) ? apb.pstrb : '0;
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assign u_user_apb4_if.paddr = |sel_i ? apb.paddr : '0;
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assign u_user_apb4_if.pprot = |sel_i ? apb.pprot : '0;
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assign u_user_apb4_if.psel = |sel_i ? apb.psel : '0;
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assign u_user_apb4_if.penable = |sel_i ? apb.penable : '0;
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assign u_user_apb4_if.pwrite = |sel_i ? apb.pwrite : '0;
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assign u_user_apb4_if.pwdata = |sel_i ? apb.pwdata : '0;
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assign u_user_apb4_if.pstrb = |sel_i ? apb.pstrb : '0;
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user_ip_top u_user_ip_top (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.sel_i (sel_i),
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.gpio (gpio),
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.apb (u_user_apb4_if)
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);
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endmodule
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