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maksyuki b5cbc89928 feat: add Tiny R2 reset distribution and feasibility analysis

- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads.
- Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves.
- Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements.
- Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts.
- Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.

2026-10-06 14:28:52 +08:00

sta

feat: add Tiny R2 reset distribution and feasibility analysis

2026-10-06 14:28:52 +08:00

syn

feat: refactor tests for mailbox and environment validation

2026-09-30 10:51:04 +08:00

README.md

feat: add Yosys synthesis scripts and update PDK paths

2026-08-14 18:51:02 +08:00

README.md

Smoke Implementation Flows

This directory contains the reproducible synthesis and static-timing source flows used by smoke and regression coverage. syn/ owns Yosys synthesis and source export; sta/ owns OpenSTA constraints and timing integration.

Generated netlists, reports, and timing artifacts remain below the selected build/<variant>/ directory. Run the flows through the root Makefile with a committed profile; do not write generated output into this source tree.