mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
71 lines
2.0 KiB
Systemverilog
71 lines
2.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// Converts Debug Module reset requests into a management-hart-only reset.
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// The request is retained until the AHB-Lite bridge has completed its current
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// AXI4 transfer, so a debugger cannot discard an accepted management access.
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module mgmt_debug_reset #(
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parameter int ResetSyncStages = 3
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic reset_req_i,
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input logic bridge_idle_i,
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output logic core_rst_n_o,
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output logic reset_done_o
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);
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logic s_pending_d, s_pending_q;
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logic s_reset_active_d, s_reset_active_q;
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always_comb begin
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s_pending_d = s_pending_q;
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s_reset_active_d = s_reset_active_q;
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if (reset_req_i) begin
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s_pending_d = 1'b1;
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end
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if (s_reset_active_q && !reset_req_i) begin
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s_pending_d = 1'b0;
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s_reset_active_d = 1'b0;
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end else if (!s_reset_active_q && s_pending_q && bridge_idle_i) begin
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s_reset_active_d = 1'b1;
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end
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end
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dffr #(
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.DATA_WIDTH(1)
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) u_pending_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_pending_d),
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.dat_o (s_pending_q)
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);
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dffr #(
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.DATA_WIDTH(1)
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) u_reset_active_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_reset_active_d),
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.dat_o (s_reset_active_q)
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);
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rst_sync #(
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.STAGE(ResetSyncStages)
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) u_core_rst_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i && !s_reset_active_q),
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.rst_n_o(core_rst_n_o)
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);
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assign reset_done_o = core_rst_n_o && !s_pending_q && !s_reset_active_q;
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endmodule
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