mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
77 lines
2.4 KiB
JSON
77 lines
2.4 KiB
JSON
{
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"schema_version": 2,
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"reset_ports": [
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"ext_rst_n_i_pad",
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"jtag_trst_n_i_pad"
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],
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"domains": [
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{
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"name": "system",
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"clock": "clk_i",
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"reset": "system_rst_n_o",
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"reset_source": "s_system_req_n",
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"reset_primitive": "rst_sync",
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"path": "rtl/tiny/top/tiny_reset_tree.sv",
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"instance": "u_system_rst_sync",
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"sta": {
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"source_port": "extclk_i_pad",
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"pin": "u_clock_buffer/clk_o",
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"period_ns": 41.666666667,
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"async_group": "system"
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}
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},
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{
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"name": "jtag",
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"clock": "s_jtag_tck_buf",
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"reset": "s_jtag_trst_n_sync",
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"reset_source": "jtag_trst_n_i",
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"reset_primitive": "rst_sync",
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"path": "rtl/ip/core/mgmt_debug_wrapper.sv",
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"instance": "u_jtag_rst_sync",
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"sta": {
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"source_port": "jtag_tck_i_pad",
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"object_type": "port",
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"period_ns": 100.0,
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"async_group": "jtag"
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}
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}
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],
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"reset_distribution": {
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"release_edges": 5,
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"por": "u_soc.u_reset_tree.u_por_rst_sync",
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"system": "u_soc.u_reset_tree.u_system_rst_sync",
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"system_source": "por_rst_n_o && !watchdog_reset_req_i",
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"leaf_instance_pattern": "u_soc.u_reset_tree.gen_leaf[%d].u_leaf_rst_sync",
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"leaf_names": [
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"fabric", "gpio", "uart0", "uart1", "timer0", "timer1", "i2c0", "i2c1",
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"xpi", "dma", "sysctrl", "clint", "sram", "archinfo", "pwm", "rtc", "wdg"
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],
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"cpu_prerequisite": "all leaf resets released",
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"hart": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_mgmt_debug_reset.u_core_rst_sync",
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"jtag": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_jtag_rst_sync",
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"dmi": "u_soc.u_cpu.u_mgmt_debug_wrapper.u_dmi_rst_sync",
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"watchdog_functional_reset": "POR only; APB uses wdg leaf",
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"main_sram_payload_reset": "none",
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"crypto": "not integrated; physical erasure contract unchanged",
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"clock_domain": "system"
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},
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"crossings": [
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{
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"name": "debug_dmi",
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"source": "jtag",
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"destination": "system",
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"primitive": "hazard3_apb_async_bridge",
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"path": "rtl/managed/hazard3/hdl/debug/dtm/hazard3_jtag_dtm_core.v",
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"instance": "inst_hazard3_apb_async_bridge"
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},
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{
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"name": "debug_hard_reset",
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"source": "jtag",
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"destination": "system",
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"primitive": "cdc_sync",
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"path": "rtl/ip/core/mgmt_debug_wrapper.sv",
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"instance": "u_dmihardreset_cdc_sync"
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}
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]
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}
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