mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
393 lines
12 KiB
Systemverilog
393 lines
12 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao
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// SPDX-License-Identifier: MulanPSL-2.0
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`include "mmap_define.svh"
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module retrosoc_tiny (
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input logic clk_i,
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input logic rst_n_i,
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input logic jtag_tck_i,
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input logic jtag_tms_i,
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input logic jtag_tdi_i,
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input logic jtag_trst_n_i,
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output logic jtag_tdo_o,
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input logic uart0_rx_i,
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output logic uart0_tx_o,
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input logic uart1_rx_i,
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output logic uart1_tx_o,
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gpio_if.soc_pad gpio,
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xpi_if.dut xpi,
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output logic test_done_o,
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output logic test_pass_o,
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output logic [7:0] test_code_o
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);
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logic s_por_rst_n, s_rst_n;
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logic [16:0] s_leaf_rst_n;
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logic s_fabric_rst_n, s_cpu_ready_rst_n;
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logic s_master_rst_n [2];
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logic s_target_rst_n [5];
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logic s_debug_halted;
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logic [31:0] s_irq;
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logic s_fault_valid, s_fault_master, s_fault_write;
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logic [31:0] s_fault_addr;
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logic [ 1:0] s_fault_resp;
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logic s_perf_enable, s_perf_clear;
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logic [63:0] s_cpu_wait, s_dma_wait;
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logic s_timer0_irq, s_timer1_irq, s_xpi_irq, s_dma_irq;
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logic s_dma_done;
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logic [7:0] s_dma_stall;
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logic [4:0] s_tick_count_d, s_tick_count_q;
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logic s_tick;
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logic s_unused_uart1_tx_stall, s_unused_uart1_rx_stall;
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`include "tiny_apb_interfaces.svh"
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uart_if u_uart0_if ();
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uart_if u_uart1_if ();
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i2c_if u_i2c0_if ();
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i2c_if u_i2c1_if ();
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pwm_if u_pwm_if ();
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clint_if u_clint_if ();
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gpio_if u_gpio_if ();
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user_gpio_if u_user_gpio_if ();
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dma_req_if u_dma_req_if ();
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rtc_if u_rtc_if (
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.rtc_clk_i (clk_i),
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.rtc_rst_n_i(s_rtc_rst_n)
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);
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// The watchdog reset pulse must survive resetting the bus/CPU. Its timer
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// uses POR reset while its APB register domain uses the system reset.
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wdg_if u_wdg_if (
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.wdg_clk_i (clk_i),
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.wdg_rst_n_i(s_por_rst_n)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) u_masters_axi4_if[2] (
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.aclk (clk_i),
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.aresetn(s_master_rst_n)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) u_targets_axi4_if[5] (
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.aclk (clk_i),
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.aresetn(s_target_rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_i2s_tx_axis_if (
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.aclk (clk_i),
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.aresetn(s_dma_rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_i2s_rx_axis_if (
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.aclk (clk_i),
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.aresetn(s_dma_rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_dvp_rx_axis_if (
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.aclk (clk_i),
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.aresetn(s_dma_rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_crypto_tx_axis_if (
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.aclk (clk_i),
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.aresetn(s_dma_rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_crypto_rx_axis_if (
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.aclk (clk_i),
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.aresetn(s_dma_rst_n)
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);
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assign s_fabric_rst_n = s_leaf_rst_n[0];
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assign s_master_rst_n = '{s_cpu_ready_rst_n, s_dma_rst_n};
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assign s_target_rst_n = '{
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s_sram_rst_n,
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s_xpi_rst_n,
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s_fabric_rst_n,
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s_fabric_rst_n,
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s_fabric_rst_n
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};
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tiny_reset_tree u_reset_tree (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.watchdog_reset_req_i(u_wdg_if.reset_req_o),
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.por_rst_n_o (s_por_rst_n),
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.system_rst_n_o (s_rst_n),
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.leaf_rst_n_o (s_leaf_rst_n),
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.cpu_ready_rst_n_o (s_cpu_ready_rst_n)
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);
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assign s_tick = s_tick_count_q == 5'd23;
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assign s_tick_count_d = s_tick ? 5'd0 : (s_tick_count_q + 5'd1);
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dffr #(
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.DATA_WIDTH(5)
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) u_tick_reg (
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.clk_i (clk_i),
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.rst_n_i(s_fabric_rst_n),
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.dat_i (s_tick_count_d),
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.dat_o (s_tick_count_q)
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);
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mgmt_core_wrapper #(
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.ExternalIrqCount (30),
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.EnableAtomics (1'b0),
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.TwoCycleBusErrors(1'b1),
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.ResetSyncStages (5)
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) u_cpu (
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.clk_i (clk_i),
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.rst_n_i (s_cpu_ready_rst_n),
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.irq_i (s_irq),
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.jtag_tck_i (jtag_tck_i),
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.jtag_tms_i (jtag_tms_i),
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.jtag_tdi_i (jtag_tdi_i),
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.jtag_trst_n_i (jtag_trst_n_i),
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.jtag_tdo_o (jtag_tdo_o),
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.debug_halted_o(s_debug_halted),
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.axi4 (u_masters_axi4_if[0])
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);
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tiny_axi4_fabric u_fabric (
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.clk_i (clk_i),
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.rst_n_i (s_fabric_rst_n),
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.masters (u_masters_axi4_if),
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.targets (u_targets_axi4_if),
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.perf_enable_i (s_perf_enable),
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.perf_clear_i (s_perf_clear),
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.fault_valid_o (s_fault_valid),
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.fault_addr_o (s_fault_addr),
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.fault_master_o(s_fault_master),
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.fault_write_o (s_fault_write),
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.fault_resp_o (s_fault_resp),
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.cpu_wait_o (s_cpu_wait),
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.dma_wait_o (s_dma_wait)
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);
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onchip_ram #(
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.CapacityKiB(128),
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.DataWidth (32),
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.IdWidth (1)
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) u_sram (
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.clk_i (clk_i),
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.rst_n_i (s_sram_rst_n),
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.mem_axi4 (u_targets_axi4_if[0]),
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.cfg_apb4 (u_sram_apb4_if),
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.perf_enable_i(s_perf_enable),
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.perf_clear_i (s_perf_clear)
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);
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apb4_xpi u_xpi (
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.clk_i (clk_i),
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.rst_n_i (s_xpi_rst_n),
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.mem_axi4 (u_targets_axi4_if[1]),
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.apb4 (u_xpi_apb4_if),
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.xpi (xpi),
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.dma_xfer_done_i(s_dma_done),
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.dma_tx_stall_o (s_dma_stall[0]),
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.dma_rx_stall_o (s_dma_stall[1]),
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.irq_o (s_xpi_irq)
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);
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tiny_axi42apb4 u_apb_bridge (
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.clk_i (clk_i),
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.rst_n_i(s_fabric_rst_n),
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.axi4 (u_targets_axi4_if[2]),
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`include "tiny_apb_connections.svh"
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);
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axi4_error_slave #(
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.Response(2'b11)
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) u_decode_error (
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.clk_i (clk_i),
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.rst_n_i(s_fabric_rst_n),
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.axi4 (u_targets_axi4_if[3])
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);
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axi4_error_slave #(
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.Response(2'b10)
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) u_protocol_error (
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.clk_i (clk_i),
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.rst_n_i(s_fabric_rst_n),
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.axi4 (u_targets_axi4_if[4])
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);
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tiny_sysctrl u_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (s_sysctrl_rst_n),
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.apb4 (u_sysctrl_apb4_if),
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.fault_valid_i (s_fault_valid),
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.fault_addr_i (s_fault_addr),
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.fault_write_i (s_fault_write),
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.fault_master_i(s_fault_master),
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.fault_resp_i (s_fault_resp),
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.cpu_wait_i (s_cpu_wait),
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.dma_wait_i (s_dma_wait),
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.rtc_wake_i (u_rtc_if.wake_o),
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.perf_enable_o (s_perf_enable),
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.perf_clear_o (s_perf_clear),
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.test_done_o (test_done_o),
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.test_pass_o (test_pass_o),
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.test_code_o (test_code_o)
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);
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tiny_archinfo u_archinfo (
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.clk_i (clk_i),
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.rst_n_i(s_archinfo_rst_n),
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.apb4 (u_archinfo_apb4_if)
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);
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apb4_gpio #(
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.HasInputCmos(gpio_pad_caps_pkg::HasInputCmos),
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.HasPullUp (gpio_pad_caps_pkg::HasPullUp),
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.HasPullDown (gpio_pad_caps_pkg::HasPullDown)
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) u_gpio (
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.clk_i (clk_i),
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.rst_n_i (s_gpio_rst_n),
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.apb4 (u_gpio_apb4_if),
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.gpio (u_gpio_if),
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.user_gpio(u_user_gpio_if)
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);
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gpio_pad_bridge u_gpio_pads (
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.inner(u_gpio_if),
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.outer(gpio)
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);
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assign u_user_gpio_if.do_o = '0;
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assign u_user_gpio_if.oe_o = '0;
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assign u_uart0_if.rx_i = uart0_rx_i;
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assign uart0_tx_o = u_uart0_if.tx_o;
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assign u_uart1_if.rx_i = uart1_rx_i;
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assign u_uart1_if.cts_n_i = 1'b0;
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assign uart1_tx_o = u_uart1_if.tx_o;
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assign u_wdg_if.debug_halted_i = s_debug_halted;
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`include "tiny_gpio.svh"
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`include "tiny_irq.svh"
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apb4_uart u_uart0 (
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.clk_i (clk_i),
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.rst_n_i (s_uart0_rst_n),
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.apb4 (u_uart0_apb4_if),
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.uart (u_uart0_if),
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.dma_tx_stall_o(s_dma_stall[2]),
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.dma_rx_stall_o(s_dma_stall[3])
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);
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apb4_i2c u_i2c0 (
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.clk_i (clk_i),
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.rst_n_i (s_i2c0_rst_n),
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.apb4 (u_i2c0_apb4_if),
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.i2c (u_i2c0_if),
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.dma_tx_stall_o(s_dma_stall[4]),
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.dma_rx_stall_o(s_dma_stall[5])
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);
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apb4_timer u_timer0 (
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.clk_i (clk_i),
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.rst_n_i (s_timer0_rst_n),
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.debug_halted_i(s_debug_halted),
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.apb4 (u_timer0_apb4_if),
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.irq_o (s_timer0_irq)
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);
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apb4_uart u_uart1 (
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.clk_i (clk_i),
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.rst_n_i (s_uart1_rst_n),
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.apb4 (u_uart1_apb4_if),
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.uart (u_uart1_if),
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.dma_tx_stall_o(s_unused_uart1_tx_stall),
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.dma_rx_stall_o(s_unused_uart1_rx_stall)
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);
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apb4_i2c u_i2c1 (
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.clk_i (clk_i),
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.rst_n_i (s_i2c1_rst_n),
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.apb4 (u_i2c1_apb4_if),
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.i2c (u_i2c1_if),
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.dma_tx_stall_o(s_dma_stall[6]),
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.dma_rx_stall_o(s_dma_stall[7])
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);
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apb4_timer u_timer1 (
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.clk_i (clk_i),
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.rst_n_i (s_timer1_rst_n),
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.debug_halted_i(s_debug_halted),
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.apb4 (u_timer1_apb4_if),
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.irq_o (s_timer1_irq)
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);
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apb4_clint u_clint (
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.clk_i (clk_i),
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.rst_n_i (s_clint_rst_n),
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.timebase_tick_i(s_tick),
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.apb4 (u_clint_apb4_if),
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.clint (u_clint_if)
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);
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apb4_pwm #(
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.PCLK_HZ(24_000_000)
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) u_pwm (
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.debug_halted_i(s_debug_halted),
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.apb4 (u_pwm_apb4_if),
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.pwm (u_pwm_if)
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);
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apb4_rtc #(
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.RTC_CLOCK_HZ(24_000_000)
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) u_rtc (
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.apb4(u_rtc_apb4_if),
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.rtc (u_rtc_if)
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);
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apb4_wdg #(
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.WDG_CLOCK_HZ (24_000_000),
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.RESET_PULSE_CYCLES(8)
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) u_watchdog (
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.apb4(u_wdg_apb4_if),
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.wdg (u_wdg_if)
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);
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apb4_dma #(
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.NumChannels (4),
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.MaxBurstBeats(16),
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.FifoDepth (32),
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.RequestMask (16'h07f9),
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.EnableStreams(1'b0)
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) u_dma (
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.clk_i (clk_i),
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.rst_n_i (s_dma_rst_n),
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.dma_xfer_done_o(s_dma_done),
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.irq_o (s_dma_irq),
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.hw_trg (u_dma_req_if),
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.apb4 (u_dma_apb4_if),
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.axi4 (u_masters_axi4_if[1]),
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.i2s_tx_axis (u_i2s_tx_axis_if),
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.i2s_rx_axis (u_i2s_rx_axis_if),
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.dvp_rx_axis (u_dvp_rx_axis_if),
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.crypto_in_axis (u_crypto_tx_axis_if),
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.crypto_out_axis(u_crypto_rx_axis_if)
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);
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assign u_dma_req_if.i2s_tx_proc = 1'b0;
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assign u_dma_req_if.i2s_rx_proc = 1'b0;
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assign u_dma_req_if.crypto_in_proc = 1'b0;
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assign u_dma_req_if.crypto_out_proc = 1'b0;
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assign u_dma_req_if.qspi_tx_proc = !s_dma_stall[0];
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assign u_dma_req_if.qspi_rx_proc = !s_dma_stall[1];
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assign u_dma_req_if.uart_tx_proc = !s_dma_stall[2];
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assign u_dma_req_if.uart_rx_proc = !s_dma_stall[3];
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assign u_dma_req_if.i2c0_tx_proc = !s_dma_stall[4];
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assign u_dma_req_if.i2c0_rx_proc = !s_dma_stall[5];
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assign u_dma_req_if.i2c1_tx_proc = !s_dma_stall[6];
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assign u_dma_req_if.i2c1_rx_proc = !s_dma_stall[7];
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assign u_i2s_rx_axis_if.tvalid = '0;
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assign u_i2s_rx_axis_if.tdata = '0;
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assign u_i2s_rx_axis_if.tstrb = '0;
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assign u_i2s_rx_axis_if.tkeep = '0;
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assign u_i2s_rx_axis_if.tlast = '0;
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assign u_i2s_rx_axis_if.tid = '0;
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assign u_i2s_rx_axis_if.tdest = '0;
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assign u_i2s_rx_axis_if.tuser = '0;
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assign u_dvp_rx_axis_if.tvalid = '0;
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assign u_dvp_rx_axis_if.tdata = '0;
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assign u_dvp_rx_axis_if.tstrb = '0;
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assign u_dvp_rx_axis_if.tkeep = '0;
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assign u_dvp_rx_axis_if.tlast = '0;
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assign u_dvp_rx_axis_if.tid = '0;
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assign u_dvp_rx_axis_if.tdest = '0;
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assign u_dvp_rx_axis_if.tuser = '0;
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assign u_crypto_rx_axis_if.tvalid = '0;
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assign u_crypto_rx_axis_if.tdata = '0;
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assign u_crypto_rx_axis_if.tstrb = '0;
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assign u_crypto_rx_axis_if.tkeep = '0;
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assign u_crypto_rx_axis_if.tlast = '0;
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assign u_crypto_rx_axis_if.tid = '0;
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assign u_crypto_rx_axis_if.tdest = '0;
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assign u_crypto_rx_axis_if.tuser = '0;
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assign u_i2s_tx_axis_if.tready = 1'b0;
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assign u_crypto_tx_axis_if.tready = 1'b0;
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endmodule
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