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https://github.com/retroSoC/retroSoC.git
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maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
51 lines
1.6 KiB
Systemverilog
51 lines
1.6 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao
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// SPDX-License-Identifier: MulanPSL-2.0
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// One SYS clock, separate reset loads. Leaf zero owns the fabric; the remaining
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// leaves follow the canonical APB target order. This is not a clock-domain split.
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module tiny_reset_tree #(
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parameter int LeafCount = 17
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic watchdog_reset_req_i,
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output logic por_rst_n_o,
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output logic system_rst_n_o,
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output logic [LeafCount-1:0] leaf_rst_n_o,
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output logic cpu_ready_rst_n_o
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);
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logic s_system_req_n;
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assign s_system_req_n = por_rst_n_o && !watchdog_reset_req_i;
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// The core/debug wrapper adds its five local release edges after every
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// functional endpoint is ready. No external peripheral clock is a prerequisite.
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assign cpu_ready_rst_n_o = &leaf_rst_n_o;
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rst_sync #(
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.STAGE(5)
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) u_por_rst_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.rst_n_o(por_rst_n_o)
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);
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rst_sync #(
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.STAGE(5)
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) u_system_rst_sync (
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.clk_i (clk_i),
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.rst_n_i(s_system_req_n),
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.rst_n_o(system_rst_n_o)
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);
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for (genvar leaf = 0; leaf < LeafCount; leaf++) begin : gen_leaf
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// Preserve independent reset drivers through the existing Yosys flow.
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// P2 validates the mapped drivers and loads; this is not a timing exception.
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(* keep = 1, keep_hierarchy = 1 *)
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rst_sync #(
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.STAGE(5)
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) u_leaf_rst_sync (
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.clk_i (clk_i),
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.rst_n_i(system_rst_n_o),
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.rst_n_o(leaf_rst_n_o[leaf])
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);
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end
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endmodule
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