mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
78 lines
1.9 KiB
Systemverilog
78 lines
1.9 KiB
Systemverilog
`timescale 1ns / 1ps
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module mgmt_debug_reset_tb #(
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parameter int ResetSyncStages = 3
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);
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logic s_clk;
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logic s_rst_n;
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logic s_reset_req;
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logic s_bridge_idle;
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logic s_core_rst_n;
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logic s_reset_done;
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always #5 s_clk = ~s_clk;
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mgmt_debug_reset #(
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.ResetSyncStages(ResetSyncStages)
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) u_mgmt_debug_reset (
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.clk_i (s_clk),
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.rst_n_i (s_rst_n),
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.reset_req_i (s_reset_req),
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.bridge_idle_i(s_bridge_idle),
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.core_rst_n_o (s_core_rst_n),
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.reset_done_o (s_reset_done)
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);
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initial begin
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s_clk = 1'b0;
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s_rst_n = 1'b0;
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s_reset_req = 1'b0;
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s_bridge_idle = 1'b1;
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repeat (2) @(posedge s_clk);
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s_rst_n = 1'b1;
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repeat (ResetSyncStages + 1) @(posedge s_clk);
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#1;
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assert (s_core_rst_n && s_reset_done)
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else $fatal(1, "initial reset release failed");
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s_bridge_idle = 1'b0;
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s_reset_req = 1'b1;
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@(posedge s_clk);
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s_reset_req = 1'b0;
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repeat (2) @(posedge s_clk);
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#1;
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assert (s_core_rst_n && !s_reset_done)
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else $fatal(1, "request did not wait for idle");
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s_bridge_idle = 1'b1;
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@(posedge s_clk);
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#1;
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assert (!s_core_rst_n && !s_reset_done)
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else $fatal(1, "core reset did not assert");
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repeat (ResetSyncStages + 1) @(posedge s_clk);
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#1;
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assert (s_core_rst_n && s_reset_done)
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else $fatal(1, "core reset did not release");
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s_reset_req = 1'b1;
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repeat (2) @(posedge s_clk);
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#1;
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assert (!s_core_rst_n && !s_reset_done)
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else $fatal(1, "held reset did not assert");
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repeat (3) @(posedge s_clk);
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#1;
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assert (!s_core_rst_n && !s_reset_done)
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else $fatal(1, "held reset released too early");
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s_reset_req = 1'b0;
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repeat (ResetSyncStages + 1) @(posedge s_clk);
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#1;
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assert (s_core_rst_n && s_reset_done)
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else $fatal(1, "held reset did not release");
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$display("management debug reset test passed");
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$finish;
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end
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endmodule
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