mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
108 lines
3.4 KiB
Systemverilog
108 lines
3.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module tiny_r2_reset_tb;
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logic s_clk = 0;
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logic s_reset_n = 1;
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logic s_watchdog = 0;
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logic s_por_n, s_system_n, s_ready_n;
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logic [16:0] s_leaf_n;
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logic s_hart_req = 0, s_idle = 1, s_core_n, s_done;
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tiny_reset_tree u_tree (
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.clk_i (s_clk),
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.rst_n_i (s_reset_n),
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.watchdog_reset_req_i(s_watchdog),
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.por_rst_n_o (s_por_n),
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.system_rst_n_o (s_system_n),
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.leaf_rst_n_o (s_leaf_n),
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.cpu_ready_rst_n_o (s_ready_n)
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);
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mgmt_debug_reset #(
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.ResetSyncStages(5)
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) u_hart (
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.clk_i (s_clk),
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.rst_n_i (s_ready_n),
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.reset_req_i (s_hart_req),
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.bridge_idle_i(s_idle),
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.core_rst_n_o (s_core_n),
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.reset_done_o (s_done)
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);
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task automatic cycle;
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#5 s_clk = 1;
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#1;
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if (s_core_n && s_leaf_n !== 17'h1ffff) $fatal(1, "CPU released before all leaves");
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#4 s_clk = 0;
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endtask
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task automatic cold_release;
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for (int edge_count = 1; edge_count <= 20; edge_count++) begin
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cycle();
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if (s_por_n !== (edge_count >= 5)) $fatal(1, "POR release edge %0d", edge_count);
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if (s_system_n !== (edge_count >= 10)) $fatal(1, "system release edge %0d", edge_count);
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if (s_leaf_n !== ((edge_count >= 15) ? 17'h1ffff : 17'd0))
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$fatal(1, "leaf release edge %0d", edge_count);
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if (s_core_n !== (edge_count >= 20)) $fatal(1, "hart release edge %0d", edge_count);
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end
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endtask
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initial begin
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// Generate a real reset edge after elaboration in four-state simulation.
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#1 s_reset_n = 0;
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#1 s_reset_n = 1;
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cold_release();
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#2 s_reset_n = 0;
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#1;
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if ({s_por_n, s_system_n, s_leaf_n, s_core_n} !== '0)
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$fatal(1, "asynchronous stopped-clock assertion failed");
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#2 s_reset_n = 1;
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#100;
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if ({s_por_n, s_system_n, s_leaf_n, s_core_n} !== '0)
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$fatal(1, "stopped clock allowed release");
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repeat (4) cycle();
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if (s_por_n) $fatal(1, "released before five edges");
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#2 s_reset_n = 0;
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#1 s_reset_n = 1;
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cold_release();
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#2 s_watchdog = 1;
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#1;
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if (!s_por_n || s_system_n || s_leaf_n != 0 || s_core_n)
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$fatal(1, "watchdog did not preserve POR and reset the system");
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repeat (8) cycle();
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s_watchdog = 0;
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for (int edge_count = 1; edge_count <= 15; edge_count++) begin
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cycle();
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if (!s_por_n || s_system_n !== (edge_count >= 5) ||
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s_leaf_n !== ((edge_count >= 10) ? 17'h1ffff : 17'd0) ||
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s_core_n !== (edge_count >= 15))
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$fatal(1, "watchdog release sequencing");
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end
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s_idle = 0;
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s_hart_req = 1;
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cycle();
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s_hart_req = 0;
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repeat (4) begin
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cycle();
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if (!s_core_n || s_done || s_leaf_n != 17'h1ffff)
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$fatal(1, "hart request discarded accepted work or reset other clients");
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end
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s_idle = 1;
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cycle();
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if (s_core_n || s_done) $fatal(1, "idle hart did not assert reset");
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cycle(); // Retained request clears; five release edges follow.
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for (int edge_count = 1; edge_count <= 5; edge_count++) begin
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cycle();
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if (s_leaf_n != 17'h1ffff || s_core_n !== (edge_count == 5))
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$fatal(1, "hart-only release or peripheral preservation failed");
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end
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if (!s_done) $fatal(1, "hart reset completion missing");
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$display("SIM_TEST_PASS Tiny R2 reset");
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$finish;
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end
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initial begin
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#10000;
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$fatal(1, "SIM_TEST_TIMEOUT Tiny R2 reset");
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end
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endmodule
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