mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
b72e14ea40
- Introduced for independent mathematical operations and RSA fixtures. - Implemented for testing DMA channels with AES ECB and memory interactions. - Created to validate RSA-2048 operations and Montgomery reduction. - Developed for testing AES and SHA vector compliance. - Added to validate image packing, integer root calculations, and inventory checks. - Ensured robust error handling and validation in tests to catch data corruption and recursive hierarchy issues.
353 lines
12 KiB
Systemverilog
353 lines
12 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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// Real DMA channels 4/5 -> AES ECB -> memory, with AXI stalls.
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`timescale 1ns / 1ps
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module crypto_dma_p0_tb;
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import dma_pkg::*;
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localparam int NumChannels = 8;
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localparam logic [31:0] SourceBase = 32'h4000_0000;
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localparam logic [31:0] DestinationBase = 32'h4000_1000;
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localparam logic [31:0] TransferBytes = 32'd64;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [NumChannels*32-1:0] ch_cfg_i = '0;
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logic [NumChannels*32-1:0] src_addr_i = '0;
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logic [NumChannels*32-1:0] dst_addr_i = '0;
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logic [NumChannels*32-1:0] byte_count_i = '0;
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logic [NumChannels*32-1:0] request_sel_i = '0;
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logic [NumChannels*32-1:0] burst_cfg_i = '0;
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logic [ NumChannels-1:0] start_i = '0;
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logic [ NumChannels-1:0] busy_o;
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logic [ NumChannels-1:0] done_o;
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logic [ NumChannels-1:0] error_o;
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logic [NumChannels*32-1:0] bytes_done_o;
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logic [ 31:0] cycle_q = '0;
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logic read_active_q = 1'b0;
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logic [ 31:0] read_addr_q = '0;
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logic [ 4:0] read_beats_q = '0;
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logic [ 4:0] read_index_q = '0;
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logic write_active_q = 1'b0;
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logic [ 31:0] write_addr_q = '0;
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logic [ 4:0] write_beats_q = '0;
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logic [ 4:0] write_index_q = '0;
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logic write_response_q = 1'b0;
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logic stream_last_seen_q = 1'b0;
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integer write_count = 0;
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logic crypto_irq, crypto_input_proc, crypto_output_proc;
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apb4_if crypto_apb (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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function automatic logic [31:0] plaintext(input logic [1:0] index);
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case (index)
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0: return 32'h33221100;
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1: return 32'h77665544;
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2: return 32'hbbaa9988;
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default: return 32'hffeeddcc;
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endcase
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endfunction
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function automatic logic [31:0] ciphertext(input logic [1:0] index);
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case (index)
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0: return 32'hd8e0c469;
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1: return 32'h30047b6a;
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2: return 32'h80b7cdd8;
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default: return 32'h5ac5b470;
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endcase
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endfunction
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task automatic apb_write(input logic [11:0] address, input logic [31:0] data);
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@(negedge clk_i);
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crypto_apb.paddr = {20'd0, address};
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crypto_apb.pwdata = data;
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crypto_apb.pstrb = 4'hf;
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crypto_apb.pwrite = 1'b1;
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crypto_apb.psel = 1'b1;
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crypto_apb.penable = 1'b0;
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@(negedge clk_i);
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crypto_apb.penable = 1'b1;
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do begin
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@(posedge clk_i);
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end while (!crypto_apb.pready);
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if (crypto_apb.pslverr) $fatal(1, "crypto DMA APB write %h", address);
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@(negedge clk_i);
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crypto_apb.psel = 1'b0;
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crypto_apb.penable = 1'b0;
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endtask
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task automatic apb_read(input logic [11:0] address, output logic [31:0] data);
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@(negedge clk_i);
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crypto_apb.paddr = {20'd0, address};
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crypto_apb.pstrb = 0;
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crypto_apb.pwrite = 1'b0;
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crypto_apb.psel = 1'b1;
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crypto_apb.penable = 1'b0;
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@(negedge clk_i);
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crypto_apb.penable = 1'b1;
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do begin
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@(posedge clk_i);
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end while (!crypto_apb.pready);
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if (crypto_apb.pslverr) $fatal(1, "crypto DMA APB read %h", address);
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data = crypto_apb.prdata;
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@(negedge clk_i);
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crypto_apb.psel = 1'b0;
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crypto_apb.penable = 1'b0;
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endtask
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initial begin
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#1000000;
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$fatal(1, "crypto DMA test watchdog");
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end
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dma_req_if req ();
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axi4_if axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_tx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if i2s_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if dvp_rx_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_in_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if crypto_out_axis (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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apb4_crypto u_crypto (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.irq_o (crypto_irq),
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.dma_input_proc_o (crypto_input_proc),
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.dma_output_proc_o(crypto_output_proc),
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.apb4 (crypto_apb),
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.crypto_in_axis (crypto_in_axis),
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.crypto_out_axis (crypto_out_axis)
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);
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always #5 clk_i = ~clk_i;
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assign req.i2s_tx_proc = 1'b1;
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assign req.i2s_rx_proc = 1'b1;
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assign req.qspi_tx_proc = 1'b1;
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assign req.qspi_rx_proc = 1'b1;
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assign req.uart_tx_proc = 1'b1;
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assign req.uart_rx_proc = 1'b1;
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assign req.i2c0_tx_proc = 1'b1;
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assign req.i2c0_rx_proc = 1'b1;
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assign req.i2c1_tx_proc = 1'b1;
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assign req.i2c1_rx_proc = 1'b1;
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assign req.crypto_in_proc = crypto_input_proc;
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assign req.crypto_out_proc = crypto_output_proc;
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assign axi4.arready = !read_active_q && cycle_q[0];
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assign axi4.rid = '0;
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assign axi4.rdata = plaintext(2'(((read_addr_q - SourceBase) >> 2) + read_index_q));
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assign axi4.rresp = `AXI4_RESP_OKAY;
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assign axi4.rlast = (read_index_q + 1'b1) == read_beats_q;
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assign axi4.ruser = '0;
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assign axi4.rvalid = read_active_q;
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assign axi4.awready = !write_active_q && !write_response_q && cycle_q[0];
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assign axi4.wready = write_active_q && cycle_q[1];
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assign axi4.bid = '0;
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assign axi4.bresp = `AXI4_RESP_OKAY;
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assign axi4.buser = '0;
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assign axi4.bvalid = write_response_q;
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assign i2s_tx_axis.tready = 1'b0;
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assign i2s_rx_axis.tdata = '0;
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assign i2s_rx_axis.tkeep = '0;
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assign i2s_rx_axis.tstrb = '0;
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assign i2s_rx_axis.tlast = 1'b0;
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assign i2s_rx_axis.tid = '0;
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assign i2s_rx_axis.tdest = '0;
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assign i2s_rx_axis.tuser = '0;
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assign i2s_rx_axis.tvalid = 1'b0;
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assign dvp_rx_axis.tdata = '0;
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assign dvp_rx_axis.tkeep = '0;
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assign dvp_rx_axis.tstrb = '0;
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assign dvp_rx_axis.tlast = 1'b0;
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assign dvp_rx_axis.tid = '0;
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assign dvp_rx_axis.tdest = '0;
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assign dvp_rx_axis.tuser = '0;
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assign dvp_rx_axis.tvalid = 1'b0;
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dma_core #(
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.NumChannels (NumChannels),
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.MaxBurstBeats(16),
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.FifoDepth (16)
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) u_dma_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.global_reset_i (1'b0),
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.global_error_clear_i (1'b0),
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.ch_cfg_i (ch_cfg_i),
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.src_addr_i (src_addr_i),
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.dst_addr_i (dst_addr_i),
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.byte_count_i (byte_count_i),
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.request_sel_i (request_sel_i),
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.burst_cfg_i (burst_cfg_i),
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.start_i (start_i),
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.suspend_i ('0),
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.resume_i ('0),
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.abort_i ('0),
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.channel_reset_i ('0),
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.event_clear_i ('0),
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.busy_o (busy_o),
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.suspended_o (),
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.done_o (done_o),
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.aborted_o (),
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.error_o (error_o),
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.stream_last_o (),
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.event_status_o (),
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.error_status_o (),
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.error_addr_o (),
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.current_src_o (),
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.current_dst_o (),
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.remaining_o (),
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.bytes_done_o (bytes_done_o),
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.stall_cycles_lo_o (),
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.stall_cycles_hi_o (),
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.first_error_valid_o (),
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.first_error_channel_o(),
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.first_error_status_o (),
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.first_error_addr_hi_o(),
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.request_status_o (),
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.xpi_xfer_done_o (),
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.req (req),
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.axi4 (axi4),
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.i2s_tx_axis (i2s_tx_axis),
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.i2s_rx_axis (i2s_rx_axis),
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.dvp_rx_axis (dvp_rx_axis),
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.crypto_in_axis (crypto_in_axis),
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.crypto_out_axis (crypto_out_axis)
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);
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always_ff @(posedge clk_i or negedge rst_n_i) begin
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if (!rst_n_i) begin
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cycle_q <= '0;
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read_active_q <= 1'b0;
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write_active_q <= 1'b0;
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write_response_q <= 1'b0;
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stream_last_seen_q <= 1'b0;
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write_count <= 0;
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end else begin
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cycle_q <= cycle_q + 1'b1;
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if (axi4.arvalid && axi4.arready) begin
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read_active_q <= 1'b1;
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read_addr_q <= axi4.araddr;
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read_beats_q <= axi4.arlen + 1'b1;
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read_index_q <= '0;
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end
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if (axi4.rvalid && axi4.rready) begin
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if (axi4.rlast) begin
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read_active_q <= 1'b0;
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end else begin
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read_index_q <= read_index_q + 1'b1;
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end
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end
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if (axi4.awvalid && axi4.awready) begin
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write_active_q <= 1'b1;
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write_addr_q <= axi4.awaddr;
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write_beats_q <= axi4.awlen + 1'b1;
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write_index_q <= '0;
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end
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if (axi4.wvalid && axi4.wready) begin
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if ((write_addr_q + (write_index_q << 2)) != (DestinationBase + (write_count * 4))) begin
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$fatal(1, "crypto DMA write address mismatch");
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end
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if (axi4.wdata != ciphertext(2'(write_count))) begin
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$fatal(1, "crypto DMA write data mismatch: %h at %0d", axi4.wdata, write_count);
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end
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write_count <= write_count + 1;
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if (axi4.wlast) begin
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if ((write_index_q + 1'b1) != write_beats_q) begin
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$fatal(1, "crypto DMA WLAST mismatch");
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end
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write_active_q <= 1'b0;
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write_response_q <= 1'b1;
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end else begin
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write_index_q <= write_index_q + 1'b1;
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end
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end
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if (axi4.bvalid && axi4.bready) begin
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write_response_q <= 1'b0;
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end
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if (crypto_in_axis.tvalid && crypto_in_axis.tready && crypto_in_axis.tlast) begin
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stream_last_seen_q <= 1'b1;
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end
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end
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end
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initial begin
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integer wait_cycles;
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logic [31:0] status;
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crypto_apb.paddr = 0;
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crypto_apb.pprot = 0;
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crypto_apb.psel = 0;
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crypto_apb.penable = 0;
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crypto_apb.pwrite = 0;
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crypto_apb.pwdata = 0;
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crypto_apb.pstrb = 0;
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ch_cfg_i[(4*32)+:32] = {22'd0, 2'd3, 1'b0, 1'b1, DMA_WIDTH_32, 1'b0, DMA_KIND_MM_TO_STREAM};
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src_addr_i[(4*32)+:32] = SourceBase;
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byte_count_i[(4*32)+:32] = TransferBytes;
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request_sel_i[(4*32)+:32] = {28'd0, DMA_REQUEST_CRYPTO_IN};
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burst_cfg_i[(4*32)+:32] = 32'd8;
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ch_cfg_i[(5*32)+:32] = {22'd0, 2'd3, 1'b1, 1'b0, DMA_WIDTH_32, 1'b0, DMA_KIND_STREAM_TO_MM};
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dst_addr_i[(5*32)+:32] = DestinationBase;
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byte_count_i[(5*32)+:32] = TransferBytes;
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request_sel_i[(5*32)+:32] = {28'd0, DMA_REQUEST_CRYPTO_OUT};
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burst_cfg_i[(5*32)+:32] = 32'd8;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_write(12'h104, 32'h100);
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apb_write(12'h140, 32'h03020100);
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apb_write(12'h144, 32'h07060504);
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apb_write(12'h148, 32'h0b0a0908);
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apb_write(12'h14c, 32'h0f0e0d0c);
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apb_write(12'h128, 32'h1);
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status = 0;
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while (!(status & 1)) apb_read(12'h12c, status);
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apb_write(12'h10c, TransferBytes);
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apb_write(12'h100, 32'h1);
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@(negedge clk_i);
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start_i[5:4] = 2'b11;
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@(negedge clk_i);
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start_i = '0;
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wait_cycles = 0;
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while (!(done_o[4] && done_o[5]) && (wait_cycles < 5000)) begin
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@(posedge clk_i);
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wait_cycles = wait_cycles + 1;
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end
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if (!(done_o[4] && done_o[5])) begin
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$fatal(1, "crypto DMA endpoint test timeout");
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end
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if ((error_o != '0) || (write_count != 16) || !stream_last_seen_q ||
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(bytes_done_o[(4*32)+:32] != TransferBytes) ||
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(bytes_done_o[(5*32)+:32] != TransferBytes)) begin
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$fatal(1, "crypto DMA result mismatch errors=%b writes=%0d last=%b", error_o, write_count,
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stream_last_seen_q);
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end
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apb_read(12'h108, status);
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if ((status & 32'h6) != 32'h2) $fatal(1, "AES DMA did not complete correctly");
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apb_read(12'h124, status);
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$display("CRYPTO_CYCLES operation=aes_dma_64bytes cycles=%0d", status);
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$display("CRYPTO_P0_DMA_PASS");
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$finish;
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end
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endmodule
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