mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
293 lines
10 KiB
Python
293 lines
10 KiB
Python
"""Tests for generated core-STA constraints."""
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from __future__ import annotations
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import hashlib
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import io
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import json
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import re
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import subprocess
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import sys
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import tarfile
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
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PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
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GENERATOR = ROOT / "physical/smoke/sta/opensta/generate_sdc.py"
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OPENSTA_MAKEFILE = ROOT / "physical/smoke/sta/opensta/opensta.mk"
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PDK_TIMING_MAKEFILE = ROOT / "physical/smoke/sta/opensta/pdk_timing.mk"
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RCU = ROOT / "rtl/mini/top/rcu.sv"
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CLOCK_SUBSYSTEM = ROOT / "rtl/mini/top/soc_clock_reset_subsystem.sv"
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RETROSOC_ASIC = ROOT / "rtl/mini/top/retrosoc_asic.sv"
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GF180_GENERATOR = ROOT / "physical/pdk/generate_gf180_liberty.py"
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ICS55_PREPARER = ROOT / "physical/pdk/prepare_ics55_liberty.py"
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ICS55_SIM_MODEL_PREPARER = ROOT / "physical/pdk/prepare_ics55_sim_model.py"
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def generate(domains: Path, output: Path) -> subprocess.CompletedProcess[str]:
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return subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--domains",
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str(domains),
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"--pin-map",
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str(PIN_MAP),
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"--output",
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str(output),
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],
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text=True,
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capture_output=True,
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)
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def test_core_sdc_covers_current_clock_domains(tmp_path: Path) -> None:
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output = tmp_path / "retrosoc_core.sdc"
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result = generate(DOMAINS, output)
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assert result.returncode == 0, result.stderr
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sdc = output.read_text(encoding="utf-8")
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assert "create_clock -name clk_aon -period 41.666666667" in sdc
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assert "create_generated_clock -name clk_lp" in sdc
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assert "create_clock -name clk_hp -period 4.166666667" in sdc
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assert "create_generated_clock -name clk_pclk" in sdc
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assert "create_clock -name clk_memory -period 27.777777778" in sdc
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assert "create_clock -name clk_audio -period 54.253472222" in sdc
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assert "create_clock -name clk_jtag -period 100" in sdc
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assert "create_clock -name clk_dvp -period 41.666666667" in sdc
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assert "create_clock -name clk_usb2_ulpi -period 16.666666667" in sdc
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assert "get_pins -quiet" in sdc
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assert "get_nets -quiet" in sdc
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assert "get_ports -quiet" in sdc
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assert (
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"set clk_lp_pin [require_net_driver_pin \"clock lp\" {s_sys_clk}]" in sdc
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)
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assert (
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"set clk_hp_pin [require_net_driver_pin \"clock hp\" {s_hp_clk}]" in sdc
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)
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assert (
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"set clk_pclk_pin [require_net_driver_pin \"clock pclk\" {s_pclk}]" in sdc
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)
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assert (
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"set clk_memory_pin [require_net_driver_pin \"clock memory\" {s_mem_clk}]" in sdc
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)
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assert "set clk_jtag_port [require_ports \"clock jtag\" {jtag_tck_i_pad}]" in sdc
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assert (
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"set clk_usb2_ulpi_port [require_ports \"clock usb2_ulpi\" "
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"{usb2_ulpi_clk_i_pad}]"
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) in sdc
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assert "u_retrosoc.u_apb4_periph.u_axi4_dvp.u_dvp_pclk_clk_buf/clk_o" in sdc
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assert "-group [get_clocks {clk_lp clk_pclk}]" in sdc
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assert "set_clock_transition 0.1 [get_clocks {clk_dvp}]" in sdc
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assert "set_input_transition" not in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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def test_audio_sdc_root_drives_the_functional_audio_domain() -> None:
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rcu = RCU.read_text(encoding="utf-8")
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subsystem = CLOCK_SUBSYSTEM.read_text(encoding="utf-8")
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asic = RETROSOC_ASIC.read_text(encoding="utf-8")
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assert re.search(r"\boutput\s+logic\s+aud_clk_o\b", rcu) is not None
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assert re.search(r"\bassign\s+aud_clk_o\s*=\s*s_aud_clk_buf\s*;", subsystem) is not None
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assert re.search(r"\.aud_clk_o\s*\(s_aud_clk_buf\)", asic) is not None
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assert re.search(r"\.clk_aud_i\s*\(s_aud_clk_buf\)", asic) is not None
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assert re.search(r"\.clk_aud_i\s*\(s_aud_clk\)", asic) is None
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def test_opensta_invocation_exits_after_a_tcl_error() -> None:
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makefile = OPENSTA_MAKEFILE.read_text(encoding="utf-8")
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assert "$(OPENSTA) -no_init -exit -threads $(OPENSTA_THREADS)" in makefile
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def test_ihp130_core_sta_loads_usb2_packet_ram_liberties() -> None:
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makefile = PDK_TIMING_MAKEFILE.read_text(encoding="utf-8")
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assert "RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib" in makefile
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assert "RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib" in makefile
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assert "OPENSTA_SRAM_LIBS := $(IHP130_USB2_SRAM_LIBS)" in makefile
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def test_open_pdk_core_sta_uses_matching_sram_corners() -> None:
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makefile = PDK_TIMING_MAKEFILE.read_text(encoding="utf-8")
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opensta = OPENSTA_MAKEFILE.read_text(encoding="utf-8")
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assert "gf180mcu_fd_ip_sram__sram512x8m8wm1__ss_125C_4v50.lib" in makefile
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assert "sky130_sram_4kbyte_1rw_32x1024_8_SS_1p4V_100C.lib" in makefile
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assert "HAVE_SRAM_MACRO=$(HAVE_SRAM_MACRO)" in opensta
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assert "SRAM_SIZE_KIB=$(SRAM_SIZE_KIB)" in opensta
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def test_core_sdc_rejects_pads_missing_from_the_pin_map(tmp_path: Path) -> None:
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document = json.loads(DOMAINS.read_text(encoding="utf-8"))
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document["domains"][0]["sta"]["source_port"] = "missing_pad"
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invalid = tmp_path / "clock_reset_domains.json"
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invalid.write_text(json.dumps(document), encoding="utf-8")
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result = generate(invalid, tmp_path / "retrosoc_core.sdc")
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assert result.returncode != 0
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assert "source port is not declared in pin map" in result.stderr
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def test_gf180_liberty_generator_assembles_requested_io_cells(tmp_path: Path) -> None:
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library = "gf180mcu_fd_io"
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corner = "ss_125C_4v50"
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source = tmp_path / "source"
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library_dir = source / "libraries" / library / "latest"
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liberty_dir = library_dir / "liberty"
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cells_dir = library_dir / "cells"
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liberty_dir.mkdir(parents=True)
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(liberty_dir / f"{library}__{corner}.lib").write_text(
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"library (gf180_io) {\n}\n", encoding="utf-8"
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)
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for cell in ("bi_t", "in_c"):
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cell_dir = cells_dir / cell
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cell_dir.mkdir(parents=True)
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(cell_dir / f"{library}__{cell}__{corner}.lib").write_text(
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f"cell ({cell}) {{}}\n", encoding="utf-8"
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)
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output_dir = tmp_path / "output"
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result = subprocess.run(
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[
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sys.executable,
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str(GF180_GENERATOR),
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"--source",
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str(source),
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"--output-dir",
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str(output_dir),
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"--revision",
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"locked-revision",
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"--library",
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library,
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"--cell",
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"bi_t",
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"--cell",
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"in_c",
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"--corner",
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corner,
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"--output-name",
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"retrosoc_io.lib",
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],
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text=True,
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capture_output=True,
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)
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assert result.returncode == 0, result.stderr
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output = output_dir / "retrosoc_io.lib"
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assert "library (gf180_io)" in output.read_text(encoding="utf-8")
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assert "cell (bi_t) {}" in output.read_text(encoding="utf-8")
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assert "cell (in_c) {}" in output.read_text(encoding="utf-8")
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assert (output.with_suffix(".lib.revision")).read_text(encoding="utf-8") == (
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"locked-revision\ngf180mcu_fd_io\nbi_t,in_c\n"
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)
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def test_ics55_liberty_preparer_selects_stable_tt_and_ss_views(tmp_path: Path) -> None:
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archive = tmp_path / "ics55_LLSC_H7CR_liberty.tar.bz2"
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members = {
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"liberty/ics55_LLSC_H7CR_tt_1p2_25c.lib": "library (ics55_tt) {}\n",
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"liberty/ics55_LLSC_H7CR_ss_1p08_125c.lib": "library (ics55_ss) {}\n",
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}
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with tarfile.open(archive, "w:bz2") as bundle:
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for name, content in members.items():
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payload = content.encode("utf-8")
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member = tarfile.TarInfo(name)
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member.size = len(payload)
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bundle.addfile(member, io.BytesIO(payload))
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output = tmp_path / "output"
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command = [
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sys.executable,
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str(ICS55_PREPARER),
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"--archive",
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str(archive),
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"--output-dir",
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str(output),
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"--revision",
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"locked-revision",
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]
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first = subprocess.run(command, text=True, capture_output=True)
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assert first.returncode == 0, first.stderr
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assert (output / "ics55_h7cr_tt.lib").read_text(encoding="utf-8") == members[
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"liberty/ics55_LLSC_H7CR_tt_1p2_25c.lib"
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]
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assert (output / "ics55_h7cr_ss.lib").read_text(encoding="utf-8") == members[
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"liberty/ics55_LLSC_H7CR_ss_1p08_125c.lib"
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]
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assert (output / ".complete").read_text(encoding="utf-8") == (
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"locked-revision\n" + hashlib.sha256(archive.read_bytes()).hexdigest() + "\n"
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)
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first_mtime = (output / "ics55_h7cr_tt.lib").stat().st_mtime_ns
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second = subprocess.run(command, text=True, capture_output=True)
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assert second.returncode == 0, second.stderr
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assert (output / "ics55_h7cr_tt.lib").stat().st_mtime_ns == first_mtime
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def test_ics55_sim_model_preparer_patches_every_h7cr_muxi2_variant(tmp_path: Path) -> None:
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cells = (
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"MUXI2X0P5H7R",
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"MUXI2X0P7H7R",
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"MUXI2X1H7R",
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"MUXI2X1P4H7R",
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"MUXI2X2H7R",
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"MUXI2X3H7R",
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"MUXI2X4H7R",
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)
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source = tmp_path / "ics55_LLSC_H7CR.v"
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source.write_text(
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"".join(
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f"module {cell} (Y, A, B, S0);\n"
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"output Y;\n"
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"input A, B, S0;\n\n"
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" udp_mux2 u0(Y, A, B, S0);\n"
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" not u1(Y, Y);\n"
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f"endmodule //{cell}\n"
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for cell in cells
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),
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encoding="utf-8",
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)
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output = tmp_path / "ics55_h7cr_functional.v"
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command = [
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sys.executable,
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str(ICS55_SIM_MODEL_PREPARER),
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"--source",
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str(source),
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"--output",
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str(output),
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"--revision",
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"locked-revision",
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]
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first = subprocess.run(command, text=True, capture_output=True)
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assert first.returncode == 0, first.stderr
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prepared = output.read_text(encoding="utf-8")
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assert prepared.startswith(
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"/* verilator lint_off DECLFILENAME */\n/* verilator lint_off SPECIFYIGN */\n"
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)
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assert prepared.endswith(
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"/* verilator lint_on SPECIFYIGN */\n/* verilator lint_on DECLFILENAME */\n"
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)
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assert prepared.count("wire muxi2_y;") == len(cells)
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assert prepared.count("udp_mux2 u0(muxi2_y, A, B, S0);") == len(cells)
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assert "not u1(Y, Y);" not in prepared
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assert (output.with_suffix(".v.revision")).read_text(encoding="utf-8") == (
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"locked-revision\n"
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+ hashlib.sha256(source.read_bytes()).hexdigest()
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+ "\n"
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+ ",".join(cells)
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+ "\n"
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)
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first_mtime = output.stat().st_mtime_ns
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second = subprocess.run(command, text=True, capture_output=True)
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assert second.returncode == 0, second.stderr
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assert output.stat().st_mtime_ns == first_mtime
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