mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
bc48cec74a
Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
510 lines
16 KiB
Systemverilog
510 lines
16 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "i2s_define.svh"
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/* verilator lint_off DECLFILENAME */
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interface i2s_if ();
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logic mclk_o;
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logic sclk_o;
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logic lrck_o;
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logic dacdat_o;
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logic adcdat_i;
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logic irq_o;
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modport dut(
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output mclk_o,
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output sclk_o,
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output lrck_o,
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output dacdat_o,
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input adcdat_i,
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output irq_o
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);
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endinterface
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/* verilator lint_on DECLFILENAME */
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module apb4_i2s (
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// verilog_format: off -- preserve reviewed column alignment
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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output logic dma_tx_stall_o,
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output logic dma_rx_stall_o,
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output logic tx_underrun_evt_o,
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output logic rx_overrun_evt_o,
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output logic rx_flush_busy_o,
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output logic lifecycle_idle_o,
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output logic lifecycle_reset_ready_o,
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apb4_if.slave apb4,
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axi4_stream_if.sink tx_axis,
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axi4_stream_if.source rx_axis,
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i2s_if.dut i2s
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// verilog_format: on
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);
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logic [31:0] s_cfg_sys;
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logic [31:0] s_cfg_aud;
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logic s_cfg_aud_v;
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logic [31:0] s_cfg_aud_q;
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logic [ 1:0] s_cmd_sys;
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logic s_cmd_v_sys;
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logic s_cmd_rdy_sys;
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logic [ 1:0] s_cmd_aud;
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logic s_cmd_v_aud;
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logic s_cmd_tx_flush;
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logic s_cmd_rx_flush;
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logic s_irq;
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logic s_stream_tx_en;
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logic s_stream_rx_en;
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logic s_tx_pio_push;
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logic [31:0] s_tx_pio_data;
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logic s_rx_pio_pop;
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logic [31:0] s_rx_pop_data;
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logic s_tx_src_valid;
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logic s_tx_src_ready;
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logic [31:0] s_tx_src_data;
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logic s_tx_dst_valid;
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logic s_tx_dst_ready;
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logic [31:0] s_tx_dst_data;
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logic s_tx_src_clear;
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logic s_tx_src_clear_busy;
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logic s_tx_dst_clear_busy;
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logic s_tx_dst_busy_sys;
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logic s_rx_src_valid;
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logic s_rx_src_ready;
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logic [31:0] s_rx_src_data;
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logic s_rx_dst_valid;
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logic s_rx_dst_ready;
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logic [31:0] s_rx_dst_data;
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logic s_rx_src_clear;
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logic s_rx_src_clear_busy;
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logic s_rx_dst_clear_busy;
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logic s_rx_src_busy_sys;
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logic [7:0] s_tx_push_cnt_d, s_tx_push_cnt_q;
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logic [7:0] s_rx_pop_cnt_d, s_rx_pop_cnt_q;
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logic [7:0] s_tx_pop_cnt_aud_d, s_tx_pop_cnt_aud_q;
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logic [7:0] s_rx_push_cnt_aud_d, s_rx_push_cnt_aud_q;
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logic [7:0] s_tx_pop_cnt_sys;
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logic s_tx_pop_cnt_sys_v;
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logic [7:0] s_rx_push_cnt_sys;
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logic s_rx_push_cnt_sys_v;
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logic [7:0] s_tx_pop_cnt_sys_d, s_tx_pop_cnt_sys_q;
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logic [7:0] s_rx_push_cnt_sys_d, s_rx_push_cnt_sys_q;
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logic [ 7:0] s_tx_level;
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logic [ 7:0] s_rx_level;
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logic s_tx_push;
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logic s_rx_pop;
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logic s_tx_flush_busy;
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logic s_rx_flush_busy;
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logic s_core_tx_valid;
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logic s_core_rx_valid;
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logic [31:0] s_core_rx_data;
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logic s_tx_underrun_aud;
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logic s_rx_overrun_aud;
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logic s_tx_underrun_tgl_d, s_tx_underrun_tgl_q;
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logic s_rx_overrun_tgl_d, s_rx_overrun_tgl_q;
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logic s_tx_underrun_re;
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logic s_tx_underrun_fe;
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logic s_rx_overrun_re;
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logic s_rx_overrun_fe;
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logic s_tx_underrun_sys;
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logic s_rx_overrun_sys;
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logic s_tx_flush_sent_d, s_tx_flush_sent_q;
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logic s_cfg_ready;
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logic [31:0] s_cfg_sent_d, s_cfg_sent_q;
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logic s_audio_used_d, s_audio_used_q;
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// A disabled host which has never enabled its PHY may change host clock
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// even when AUDIO is absent. After use, require the disabled configuration
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// to reach AUDIO, empty FIFOs, and completed flush acknowledgements.
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assign s_cfg_sent_d = s_cfg_ready ? s_cfg_sys : s_cfg_sent_q;
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assign s_audio_used_d = s_audio_used_q || s_cfg_sys[`APB4_I2S__CFG_ENABLE];
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assign lifecycle_reset_ready_o = s_tx_src_ready && !s_tx_flush_busy && !s_rx_flush_busy;
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assign lifecycle_idle_o = !s_cfg_sys[`APB4_I2S__CFG_ENABLE] &&
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!s_stream_tx_en && !s_stream_rx_en &&
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(!s_audio_used_q || ((s_cfg_sent_q == s_cfg_sys) && s_cfg_ready &&
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s_tx_level == 0 && s_rx_level == 0 && !s_tx_flush_busy && !s_rx_flush_busy));
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dffr #(
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.DATA_WIDTH(32)
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) u_cfg_sent (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_cfg_sent_d),
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.dat_o (s_cfg_sent_q)
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);
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dffr #(
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.DATA_WIDTH(1)
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) u_audio_used (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_audio_used_d),
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.dat_o (s_audio_used_q)
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);
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assign s_cmd_sys = {s_cmd_rx_flush, s_cmd_tx_flush};
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assign s_tx_src_clear = s_cmd_tx_flush && !s_tx_flush_sent_q && !s_tx_src_clear_busy;
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assign s_rx_src_clear = s_cmd_v_aud && s_cmd_aud[`APB4_I2S__COMMAND_RX_FLUSH] &&
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!s_rx_src_clear_busy;
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assign s_tx_flush_busy = s_cmd_tx_flush || s_tx_src_clear_busy || s_tx_dst_busy_sys;
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assign s_rx_flush_busy = s_cmd_rx_flush || s_rx_dst_clear_busy || s_rx_src_busy_sys;
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assign s_tx_underrun_sys = s_tx_underrun_re || s_tx_underrun_fe;
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assign s_rx_overrun_sys = s_rx_overrun_re || s_rx_overrun_fe;
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assign rx_flush_busy_o = s_rx_flush_busy;
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assign tx_underrun_evt_o = s_tx_underrun_sys;
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assign rx_overrun_evt_o = s_rx_overrun_sys;
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assign s_tx_push = s_tx_src_valid && s_tx_src_ready;
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assign s_rx_pop = s_rx_dst_valid && s_rx_dst_ready;
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assign s_tx_level = s_tx_flush_busy ? 8'd0 : (s_tx_push_cnt_q - s_tx_pop_cnt_sys_q);
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assign s_rx_level = s_rx_flush_busy ? 8'd0 : (s_rx_push_cnt_sys_q - s_rx_pop_cnt_q);
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assign s_tx_src_data = s_stream_tx_en ? tx_axis.tdata : s_tx_pio_data;
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assign s_tx_src_valid = !s_tx_flush_busy && (s_stream_tx_en ? tx_axis.tvalid : s_tx_pio_push);
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assign tx_axis.tready = s_stream_tx_en && s_tx_src_ready && !s_tx_flush_busy;
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assign s_tx_dst_ready = s_core_tx_valid;
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assign s_rx_src_valid = s_core_rx_valid;
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assign s_rx_src_data = s_core_rx_data;
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assign s_rx_dst_ready = !s_rx_flush_busy && (s_stream_rx_en ? rx_axis.tready : s_rx_pio_pop);
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assign s_rx_pop_data = s_rx_dst_data;
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assign rx_axis.tdata = s_rx_dst_data;
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assign rx_axis.tkeep = '1;
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assign rx_axis.tstrb = '1;
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assign rx_axis.tlast = 1'b0;
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assign rx_axis.tid = '0;
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assign rx_axis.tdest = '0;
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assign rx_axis.tuser = '0;
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assign rx_axis.tvalid = s_stream_rx_en && s_rx_dst_valid && !s_rx_flush_busy;
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i2s_reg u_i2s_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (apb4),
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.tx_full_i (!s_tx_src_ready),
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.tx_empty_i (s_tx_level == 8'd0),
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.tx_level_i (s_tx_level),
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.rx_full_i (s_rx_src_busy_sys),
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.rx_empty_i (!s_rx_dst_valid),
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.rx_level_i (s_rx_level),
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.tx_flush_busy_i (s_tx_flush_busy),
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.rx_flush_busy_i (s_rx_flush_busy),
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.tx_underrun_i (s_tx_underrun_sys),
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.rx_overrun_i (s_rx_overrun_sys),
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.tx_push_valid_o (s_tx_pio_push),
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.tx_push_data_o (s_tx_pio_data),
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.rx_pop_valid_o (s_rx_pio_pop),
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.rx_pop_data_i (s_rx_pop_data),
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.cfg_o (s_cfg_sys),
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.cmd_tx_flush_o (s_cmd_tx_flush),
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.cmd_rx_flush_o (s_cmd_rx_flush),
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.cmd_valid_o (s_cmd_v_sys),
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.cmd_ready_i (s_cmd_rdy_sys),
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.stream_tx_enable_o(s_stream_tx_en),
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.stream_rx_enable_o(s_stream_rx_en),
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.dma_tx_stall_o (dma_tx_stall_o),
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.dma_rx_stall_o (dma_rx_stall_o),
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.irq_o (s_irq)
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);
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/* verilator lint_off PINCONNECTEMPTY */
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cdc_2phase #(
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.DATA_WIDTH(32)
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) u_i2s_cfg_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.src_data_i (s_cfg_sys),
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.src_valid_i(1'b1),
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.src_ready_o(s_cfg_ready),
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.dst_clk_i (clk_aud_i),
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.dst_rst_n_i(rst_aud_n_i),
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.dst_data_o (s_cfg_aud),
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.dst_valid_o(s_cfg_aud_v),
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.dst_ready_i(1'b1)
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);
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dffer #(
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.DATA_WIDTH(32)
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) u_cfg_aud_dffer (
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.clk_i (clk_aud_i),
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.rst_n_i(rst_aud_n_i),
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.en_i (s_cfg_aud_v),
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.dat_i (s_cfg_aud),
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.dat_o (s_cfg_aud_q)
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);
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cdc_2phase #(
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.DATA_WIDTH(2)
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) u_i2s_cmd_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.src_data_i (s_cmd_sys),
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.src_valid_i(s_cmd_v_sys),
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.src_ready_o(s_cmd_rdy_sys),
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.dst_clk_i (clk_aud_i),
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.dst_rst_n_i(rst_aud_n_i),
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.dst_data_o (s_cmd_aud),
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.dst_valid_o(s_cmd_v_aud),
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.dst_ready_i(!s_rx_src_clear_busy)
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);
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/* verilator lint_on PINCONNECTEMPTY */
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (32),
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.BUFFER_DEPTH(128)
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) u_tx_cdc_fifo (
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.src_clk_i (clk_i),
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.src_rst_n_i (rst_n_i),
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.src_clear_i (s_tx_src_clear),
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.src_clear_busy_o(s_tx_src_clear_busy),
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.src_data_i (s_tx_src_data),
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.src_valid_i (s_tx_src_valid),
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.src_ready_o (s_tx_src_ready),
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.dst_clk_i (clk_aud_i),
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.dst_rst_n_i (rst_aud_n_i),
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.dst_clear_busy_o(s_tx_dst_clear_busy),
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.dst_data_o (s_tx_dst_data),
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.dst_valid_o (s_tx_dst_valid),
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.dst_ready_i (s_tx_dst_ready)
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);
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (32),
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.BUFFER_DEPTH(128)
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) u_rx_cdc_fifo (
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.src_clk_i (clk_aud_i),
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.src_rst_n_i (rst_aud_n_i),
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.src_clear_i (s_rx_src_clear),
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.src_clear_busy_o(s_rx_src_clear_busy),
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.src_data_i (s_rx_src_data),
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.src_valid_i (s_rx_src_valid),
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.src_ready_o (s_rx_src_ready),
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.dst_clk_i (clk_i),
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.dst_rst_n_i (rst_n_i),
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.dst_clear_busy_o(s_rx_dst_clear_busy),
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.dst_data_o (s_rx_dst_data),
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.dst_valid_o (s_rx_dst_valid),
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.dst_ready_i (s_rx_dst_ready)
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);
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(1)
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) u_tx_dst_busy_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_tx_dst_clear_busy),
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.dat_o (s_tx_dst_busy_sys)
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);
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(1)
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) u_rx_src_busy_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (!s_rx_src_ready || s_rx_src_clear_busy),
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.dat_o (s_rx_src_busy_sys)
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);
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always_comb begin
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s_tx_push_cnt_d = s_tx_push_cnt_q;
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if (s_tx_flush_busy) s_tx_push_cnt_d = '0;
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else if (s_tx_push) s_tx_push_cnt_d = s_tx_push_cnt_q + 8'd1;
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end
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always_comb begin
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s_rx_pop_cnt_d = s_rx_pop_cnt_q;
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if (s_rx_flush_busy) s_rx_pop_cnt_d = '0;
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else if (s_rx_pop) s_rx_pop_cnt_d = s_rx_pop_cnt_q + 8'd1;
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end
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dffr #(
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.DATA_WIDTH(8)
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) u_tx_push_cnt_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_tx_push_cnt_d),
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.dat_o (s_tx_push_cnt_q)
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);
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dffr #(
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.DATA_WIDTH(8)
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) u_rx_pop_cnt_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_rx_pop_cnt_d),
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.dat_o (s_rx_pop_cnt_q)
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);
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always_comb begin
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s_tx_pop_cnt_aud_d = s_tx_pop_cnt_aud_q;
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if (s_cmd_v_aud && s_cmd_aud[`APB4_I2S__COMMAND_TX_FLUSH]) s_tx_pop_cnt_aud_d = '0;
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else if (s_tx_dst_valid && s_tx_dst_ready) s_tx_pop_cnt_aud_d = s_tx_pop_cnt_aud_q + 8'd1;
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end
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always_comb begin
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s_rx_push_cnt_aud_d = s_rx_push_cnt_aud_q;
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if (s_cmd_v_aud && s_cmd_aud[`APB4_I2S__COMMAND_RX_FLUSH]) s_rx_push_cnt_aud_d = '0;
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else if (s_rx_src_valid && s_rx_src_ready) s_rx_push_cnt_aud_d = s_rx_push_cnt_aud_q + 8'd1;
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end
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dffr #(
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.DATA_WIDTH(8)
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) u_tx_pop_cnt_aud_dffr (
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.clk_i (clk_aud_i),
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.rst_n_i(rst_aud_n_i),
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.dat_i (s_tx_pop_cnt_aud_d),
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.dat_o (s_tx_pop_cnt_aud_q)
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);
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dffr #(
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.DATA_WIDTH(8)
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) u_rx_push_cnt_aud_dffr (
|
|
.clk_i (clk_aud_i),
|
|
.rst_n_i(rst_aud_n_i),
|
|
.dat_i (s_rx_push_cnt_aud_d),
|
|
.dat_o (s_rx_push_cnt_aud_q)
|
|
);
|
|
|
|
/* verilator lint_off PINCONNECTEMPTY */
|
|
cdc_2phase #(
|
|
.DATA_WIDTH(8)
|
|
) u_tx_pop_cnt_cdc (
|
|
.src_clk_i (clk_aud_i),
|
|
.src_rst_n_i(rst_aud_n_i),
|
|
.src_data_i (s_tx_pop_cnt_aud_q),
|
|
.src_valid_i(1'b1),
|
|
.src_ready_o(),
|
|
.dst_clk_i (clk_i),
|
|
.dst_rst_n_i(rst_n_i),
|
|
.dst_data_o (s_tx_pop_cnt_sys),
|
|
.dst_valid_o(s_tx_pop_cnt_sys_v),
|
|
.dst_ready_i(1'b1)
|
|
);
|
|
cdc_2phase #(
|
|
.DATA_WIDTH(8)
|
|
) u_rx_push_cnt_cdc (
|
|
.src_clk_i (clk_aud_i),
|
|
.src_rst_n_i(rst_aud_n_i),
|
|
.src_data_i (s_rx_push_cnt_aud_q),
|
|
.src_valid_i(1'b1),
|
|
.src_ready_o(),
|
|
.dst_clk_i (clk_i),
|
|
.dst_rst_n_i(rst_n_i),
|
|
.dst_data_o (s_rx_push_cnt_sys),
|
|
.dst_valid_o(s_rx_push_cnt_sys_v),
|
|
.dst_ready_i(1'b1)
|
|
);
|
|
/* verilator lint_on PINCONNECTEMPTY */
|
|
|
|
always_comb begin
|
|
s_tx_flush_sent_d = s_tx_flush_sent_q;
|
|
if (!s_cmd_tx_flush) s_tx_flush_sent_d = 1'b0;
|
|
else if (s_tx_src_clear) s_tx_flush_sent_d = 1'b1;
|
|
end
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_tx_flush_sent_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_tx_flush_sent_d),
|
|
.dat_o (s_tx_flush_sent_q)
|
|
);
|
|
|
|
always_comb begin
|
|
s_tx_pop_cnt_sys_d = s_tx_pop_cnt_sys_q;
|
|
if (s_tx_flush_busy) s_tx_pop_cnt_sys_d = '0;
|
|
else if (s_tx_pop_cnt_sys_v) s_tx_pop_cnt_sys_d = s_tx_pop_cnt_sys;
|
|
end
|
|
always_comb begin
|
|
s_rx_push_cnt_sys_d = s_rx_push_cnt_sys_q;
|
|
if (s_rx_flush_busy) s_rx_push_cnt_sys_d = '0;
|
|
else if (s_rx_push_cnt_sys_v) s_rx_push_cnt_sys_d = s_rx_push_cnt_sys;
|
|
end
|
|
dffr #(
|
|
.DATA_WIDTH(8)
|
|
) u_tx_pop_cnt_sys_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_tx_pop_cnt_sys_d),
|
|
.dat_o (s_tx_pop_cnt_sys_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(8)
|
|
) u_rx_push_cnt_sys_dffr (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_rx_push_cnt_sys_d),
|
|
.dat_o (s_rx_push_cnt_sys_q)
|
|
);
|
|
|
|
assign s_tx_underrun_tgl_d = s_tx_underrun_aud ? ~s_tx_underrun_tgl_q : s_tx_underrun_tgl_q;
|
|
assign s_rx_overrun_tgl_d = s_rx_overrun_aud ? ~s_rx_overrun_tgl_q : s_rx_overrun_tgl_q;
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_tx_underrun_tgl_dffr (
|
|
.clk_i (clk_aud_i),
|
|
.rst_n_i(rst_aud_n_i),
|
|
.dat_i (s_tx_underrun_tgl_d),
|
|
.dat_o (s_tx_underrun_tgl_q)
|
|
);
|
|
dffr #(
|
|
.DATA_WIDTH(1)
|
|
) u_rx_overrun_tgl_dffr (
|
|
.clk_i (clk_aud_i),
|
|
.rst_n_i(rst_aud_n_i),
|
|
.dat_i (s_rx_overrun_tgl_d),
|
|
.dat_o (s_rx_overrun_tgl_q)
|
|
);
|
|
|
|
/* verilator lint_off PINCONNECTEMPTY */
|
|
edge_det #(
|
|
.STAGE(2)
|
|
) u_tx_underrun_event (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_tx_underrun_tgl_q),
|
|
.dat_o (),
|
|
.re_o (s_tx_underrun_re),
|
|
.fe_o (s_tx_underrun_fe)
|
|
);
|
|
edge_det #(
|
|
.STAGE(2)
|
|
) u_rx_overrun_event (
|
|
.clk_i (clk_i),
|
|
.rst_n_i(rst_n_i),
|
|
.dat_i (s_rx_overrun_tgl_q),
|
|
.dat_o (),
|
|
.re_o (s_rx_overrun_re),
|
|
.fe_o (s_rx_overrun_fe)
|
|
);
|
|
/* verilator lint_on PINCONNECTEMPTY */
|
|
|
|
i2s_core u_i2s_core (
|
|
.clk_i (clk_aud_i),
|
|
.rst_n_i (rst_aud_n_i),
|
|
.enable_i (s_cfg_aud_q[`APB4_I2S__CFG_ENABLE]),
|
|
.tx_enable_i (s_cfg_aud_q[`APB4_I2S__CFG_TX_ENABLE]),
|
|
.rx_enable_i (s_cfg_aud_q[`APB4_I2S__CFG_RX_ENABLE]),
|
|
.loopback_i (s_cfg_aud_q[`APB4_I2S__CFG_LOOPBACK]),
|
|
.clk_prog_i (s_cfg_aud_q[`APB4_I2S__CFG_CLK_PROG]),
|
|
.format_i (s_cfg_aud_q[`APB4_I2S__CFG_FORMAT]),
|
|
.bitmode_i (s_cfg_aud_q[`APB4_I2S__CFG_BITMODE]),
|
|
.sclk_div_i (s_cfg_aud_q[`APB4_I2S__CFG_SCLK_LSB+:8]),
|
|
.lrck_div_i (s_cfg_aud_q[`APB4_I2S__CFG_LRCK_LSB+:8]),
|
|
.mclk_div_i (s_cfg_aud_q[`APB4_I2S__CFG_MCLK_LSB+:8]),
|
|
.irq_i (s_irq),
|
|
.tx_valid_o (s_core_tx_valid),
|
|
.tx_data_i (s_tx_dst_data),
|
|
.tx_empty_i (!s_tx_dst_valid),
|
|
.rx_valid_o (s_core_rx_valid),
|
|
.rx_data_o (s_core_rx_data),
|
|
.rx_full_i (!s_rx_src_ready),
|
|
.tx_underrun_o(s_tx_underrun_aud),
|
|
.rx_overrun_o (s_rx_overrun_aud),
|
|
.i2s (i2s)
|
|
);
|
|
endmodule
|