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Integrate the Tiny RCU, normalized REF24 control, external-input profiles, single PLL backend, SYS/MEM/PCLK clocks, CPU-only WFI gating, peripheral lifecycle control and retained debug behavior. Keep CPU and all 32 main SRAM macros on SYS and the six private Crypto macros on PCLK. Add the handwritten RCU register/HAL contract, RS_EBUSY, bounded SDK operations and focused firmware. Preserve shared-IP defaults and the ICS55/PLL SAFE24 boot and explicit IHP130/no-PLL compatibility profiles. Use APB/AXI domain bridges and source-owned response holders to preserve backpressured responses, complete aborted bursts and prevent stale replay. Verify production DMA source-reset drain and common XPI endpoint reset with extracted integration bindings and an independent scoreboard. Add source-bound macro/clock audits, SAFE24 observational STA constraints and commercial-adapter host checks. No P8 functionality or operating-point qualification is included. See TINY-R2-P7 in docs/ip/tiny-soc.md. Validation: 54 P7 directed tests pass, including both simulators, ten source-reset ratio runs and two expected-negative drain mutations. RTL format/style, clock/reset inventory, Ruff and both Tiny PDK PR dry-runs pass. Retained 06-00 synthesis and strict netlist boots pass for both PDKs; STA remains negative and observational. Source comparison confirms only the follow-up tests changed after that backend campaign. Evidence: build/ics55-tiny-2026-10-14-06-00-ff4b5cef6eb5/meta/ tiny-r2-p7-source-reset/summary.json. Earlier firmware, HAL and compatibility results and the non-clean full-suite attempt retain their original attribution. Full Icarus firmware is deferred to final Tiny qualification; this commit does not constitute human phase acceptance or physical signoff.
Repository Tests
This directory contains tests for deterministic SDK behavior and build/quality tooling.
c/test_runtime.cis the host C test program used bymake sw-host-test.test_npu_framework_reference.pychecks model-specific Softmax scaling, all 65536 VWW two-class input combinations, seeded KWS vectors, unchanged hardware artifacts and complete sample-model outputs against the locked TFLite integer kernels. The C++ adapter undercpp/is host verification code, not an embedded runtime or an alternative production datapath.test_npu_qualification.pyproves that common-mode Python errors, missing oracle tools, stale source revisions and incomplete tensor records fail closed. Full corpus qualification is the explicitnpu-p0-qualifytarget; ordinary Pytest results alone do not establish full-corpus acceptance.test_npu_compiler.pycovers all ABI-1 placements, branching ADD lifetime, pooling/Clamp, malformed input, reproducible deployment packages, strict host compilation and generated C Softmax vectors.npu-p5-rtlseparately runs the prescribed KWS/VWW inputs on Icarus and Verilator with per-layer write traces;npu-p5-lp-simandnpu-p5-hp-simestablish the two bare-metal submission paths and SYSCTRL verdicts.test_npu_p6.pychecks deterministic corpus framing and CRCs, exact PRODUCT UART record parsing, cycle-accounting consistency, and fail-closed 1000-case/2x report rules. Thenpu-p6-*targets, rather than Pytest alone, produce formal, PRODUCT Verilator, synthesized-block, physical and regression evidence.test_script_tools.pycovers setup, dependency, filelist, warning, metric, archive, and regression-helper behavior.test_agent_skills.pychecks feature and engineering-workflow skill metadata, local references, eval corpora, default invocation contracts, and documented entrypoints. Run it withpython3 -m pytest -q tests/test_agent_skills.py. These are static checks; the eval corpus is reusable scenario data, not proof that an agent executed publication, dependency, or hardware workflows.test_rtl_readiness.pycovers the machine-readable RTL maturity and synthesis-intent checks.test_rtl_style.pycovers ownership, named connections, and staged naming rules for new owned RTL.test_crypto.pyruns directed AES, SHA-2, RSA/Montgomery, streaming, and APB4 V1 reference simulations plus the V2 public lifecycle fixture;test_crypto_register_parity.pychecks the handwritten RTL/C register ABI andtest_dma.pycovers DMA bursts, TCD fetch, CRC, tail-byte writes, and crypto endpoints.test_crypto_p0.pychecks the independent mathematical constant oracle, corruption rejection and hierarchy-multiplicity/register accounting.make CONFIG=configs/ci/ihp130.mk SYNTH=YOSYS crypto-p0-rtlruns the V1 baseline without invoking Pytest: real Crypto/DMA channel 4/5 traffic, AES CBC/CTR tails, SHA-224/256 padding boundaries and RSA-2048 including equal-schedule private-result verification failure. The deterministic RSA key material is public test data. These are baseline measurements, not V2 initialization/scrub or physical qualification.crypto-p1-rtlexercises V2 public initialization and rejection paths, AES key sizes/directions/multiblock/tails, SHA padding, full RSA-2048, held-output abort, concurrent engines, reset boundaries, injected readback and scrub faults, and physical FIFO/bank erasure inspection. Separatecrypto_storage_tb.svandcrypto_dma_v2_tb.svfixtures check all banks, masks, retirements, full-width Montgomery carries and actual DMA 4/5.c/crypto_firmware.cis the focused full-SoC LP HAL/DMA acceptance image; its explicit build invocation is in the Crypto specification. It never preloads Crypto SRAM through hierarchy or replaces hardware algorithms. Review-fix cases cover consecutive-command DONE, CRC-neutral padding faults, initialization timeout/lock boundaries, fatal-fault output drain and real DMA AXI read/write errors.crypto_stream_formal.svsupplements the APB, lifecycle, RSA-release and scrub proofs with arbitrary output backpressure.test_crypto_p1_evidence.pychecks that stale source/logs or a failed command cannot qualify an earlier firmware PASS; these Pytest cases are not run when the maintainer has disabled Pytest.crypto_response_fault_tb.svindependently checks delayed, duplicate, stale-epoch and missing SRAM responses while the default product store keeps its fixed one-cycle behavior.crypto_response_fault_tb.svindependently checks delayed, duplicate, stale-epoch and missing SRAM responses while the default product store keeps its fixed one-cycle behavior.test_apu.pychecks the fail-closed APU APB4/IRQ shell plus the P2 private DMA, ring scheduler, stream router, Gateway A, and verification-only backend;test_apu_register_parity.pykeeps its handwritten RTL/C ABI and matrix coverage synchronized.test_apu_primitives.pycompares the P4 assembler, BAM, loader, sequencer, local SRAM, FIFOs, and production primitive engines with Icarus and Verilator while keeping its injectors out of product filelists.test_apu_codecs.pyandtest_apu_codec_transport.pycheck the P5 target, deterministic coefficient/APUMC artifacts, integer WAV/FLAC and PCM models, direct/ring product paths, and identical Icarus/Verilator execution of the production class-6 transport. The explicitapu-p5-corpustarget qualifies every pinned official FLAC file against locked libFLAC and records matching released-APUMC production results from identical verification-only Icarus and Verilator fixtures.test_apu_p9_coefficients.pychecks the frozen APUC hashes and complete logical-to-bank inverse map with an independent frozen oracle.test_apu_p9_storage.pyruns the synchronous coefficient clients and macro-memo clear/insert/lookup boundary fixture; the P8 quiesced-loader test covers the successful integrated APUC DMA and readback path. The full corruption/retry/reset/abort lifecycle remains a separate required P9 evidence matrix and is not inferred from that smoke.test_apu_p8_quiesce_load.pydrives the fullapb4_apushell and checks that MICROCODE_LOAD and MODEL_LOAD DMA fetches are admitted and complete while the LP quiesce is held (the APU-P8 loader-admission regression).test_user_ip_register_parity.pykeeps the integrated slot 1 timer and slot 2 GPIO register offsets synchronized with their application-owned C definitions and checks their extension-manifest slot assignments.test_lp_irq.pychecks the 64-bit LP vector, 62-input metadata, Xh3irq wrapper/backend contract, CSR-disabled stubs, and generated routing.test_hp_boot_bundle.pychecks the HP flash ABI, CRCs, payload placement, and handwritten mailbox RTL/C offset parity.test_hp_platform.py,test_hp_mailbox.py,test_plic.py, and the AXI tests cover the remaining HP integration contracts.test_xpi_fast_flash.pycovers the explicitly selected Verilator slot-0 read accelerator, including backpressure and negative completion paths.
Add a host C test when changing deterministic runtime or media logic; add a Python test when changing scripts or build policy. Run:
make sw-host-test
python3 -m pytest -q
These tests complement, but do not replace, firmware builds, RTL simulation, synthesis, timing, or hardware validation.