mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
bef5881149
- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers. - Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance. - Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands. - Created spill_register_tb to verify the functionality of the spill register under various conditions. - Modified test_dma.py to reflect changes in DMA error handling and performance reporting. - Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities. - Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior. - Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces. - Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
114 lines
2.8 KiB
Systemverilog
114 lines
2.8 KiB
Systemverilog
`timescale 1ns / 1ps
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module spill_register_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic flush_i = 1'b0;
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logic valid_i = 1'b0;
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logic ready_o;
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logic [31:0] data_i = '0;
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logic valid_o;
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logic ready_i = 1'b0;
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logic [31:0] data_o;
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logic [31:0] expected [0:511];
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integer head = 0;
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integer tail = 0;
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integer cycle;
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logic held_valid = 1'b0;
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logic [31:0] held_data = '0;
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logic [31:0] lfsr = 32'h1ACE_B00C;
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always #5 clk_i = ~clk_i;
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spill_register #(
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.DATA_WIDTH(32),
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.BYPASS (1'b0)
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) u_dut (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.flush_i(flush_i),
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.valid_i(valid_i),
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.ready_o(ready_o),
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.data_i (data_i),
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.valid_o(valid_o),
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.ready_i(ready_i),
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.data_o (data_o)
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);
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task automatic check_cycle;
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begin
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@(posedge clk_i);
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if (held_valid && (!valid_o || (data_o !== held_data))) begin
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$fatal(1, "spill register changed output while stalled");
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end
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if (valid_o && ready_i) begin
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if (head == tail || data_o !== expected[head]) begin
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$fatal(1, "spill register output ordering failure");
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end
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head = head + 1;
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end
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if (valid_i && ready_o) begin
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expected[tail] = data_i;
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tail = tail + 1;
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end
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if (flush_i) begin
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head = tail;
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end
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held_valid = valid_o && !ready_i && !flush_i;
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held_data = data_o;
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end
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endtask
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initial begin
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repeat (2) @(posedge clk_i);
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@(negedge clk_i);
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rst_n_i = 1'b1;
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// Sustained one-word-per-cycle traffic exercises simultaneous push/pop.
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for (cycle = 0; cycle < 16; cycle = cycle + 1) begin
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valid_i = 1'b1;
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ready_i = 1'b1;
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data_i = 32'h1000_0000 + cycle;
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check_cycle();
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@(negedge clk_i);
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end
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// Fill both entries, hold the output, and check stability under pressure.
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ready_i = 1'b0;
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for (cycle = 0; cycle < 8; cycle = cycle + 1) begin
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valid_i = 1'b1;
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data_i = 32'h2000_0000 + cycle;
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check_cycle();
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@(negedge clk_i);
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end
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valid_i = 1'b0;
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flush_i = 1'b1;
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check_cycle();
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@(negedge clk_i);
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flush_i = 1'b0;
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// Deterministic randomized backpressure covers all occupancy transitions.
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for (cycle = 0; cycle < 256; cycle = cycle + 1) begin
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lfsr = {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
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valid_i = lfsr[0] | lfsr[3];
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ready_i = lfsr[1] | lfsr[5];
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data_i = 32'h3000_0000 + cycle;
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check_cycle();
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@(negedge clk_i);
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end
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valid_i = 1'b0;
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ready_i = 1'b1;
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while (head != tail || valid_o) begin
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check_cycle();
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@(negedge clk_i);
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end
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$display("spill register ready/valid test passed");
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$finish;
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end
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endmodule
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