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- Updated dma_error_tb to implement burst transfer handling and performance measurement for INCR4 transfers. - Introduced rib_burst_bus_tb to validate RIB burst arbitration and protocol compliance. - Added soc_rib_burst_ram_tb to test SRAM behavior with burst commands. - Created spill_register_tb to verify the functionality of the spill register under various conditions. - Modified test_dma.py to reflect changes in DMA error handling and performance reporting. - Updated test_memory_map.py to include new RIB burst interfaces and spill register utilities. - Enhanced test_rib_burst.py with directed tests for RIB burst building blocks and spill register behavior. - Adjusted test_soc_topology.py to ensure correct instantiation counts for RIB interfaces. - Improved test_user_extensions.py to validate the generation of isolated scalar bindings for burst interfaces.
54 lines
1.7 KiB
Python
54 lines
1.7 KiB
Python
"""Tests for the machine-readable benchmark log parser."""
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from __future__ import annotations
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from scripts.parse_performance_log import parse_log
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def test_parse_log_requires_terminal_marker_and_complete_samples() -> None:
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report = parse_log(
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"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
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"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
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"PERF_BENCHMARK_PASS\n"
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)
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assert report["status"] == "passed"
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assert report["failure_marker"] is False
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assert report["pass_marker"] is True
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assert report["samples"] == [
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{
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"checksum": 0x1234,
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"cycles": 123,
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"dma_wait": 0,
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"flash_wait": 0,
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"mgmt_wait": 10,
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"rib_wait": 9,
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"operation": "read",
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"psram_wait": 0,
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"region": "sdram",
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"sdram_wait": 8,
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"words": 1024,
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}
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]
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def test_parse_log_rejects_missing_benchmark_marker() -> None:
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report = parse_log(
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"PERF region=flash op=read words=1024 checksum=0 cycles=10 mgmt_wait=1 rib_wait=1 "
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"sdram_wait=0 psram_wait=0 flash_wait=1 dma_wait=0\n"
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)
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assert report["status"] == "failed"
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def test_parse_log_rejects_report_with_performance_failure() -> None:
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report = parse_log(
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"PERF region=sdram op=read words=1024 checksum=0x1234 cycles=123 mgmt_wait=10 "
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"rib_wait=9 sdram_wait=8 psram_wait=0 flash_wait=0 dma_wait=0\n"
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"PERF_FAIL region=sdram op=read reason=data expected=1234 actual=0\n"
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"PERF_BENCHMARK_PASS\n"
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)
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assert report["status"] == "failed"
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assert report["failure_marker"] is True
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