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maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
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1.4 KiB
Physical Design
This directory owns physical-design integration, managed technology inputs, smoke implementation-flow sources, and the self-developed commercial-flow drivers.
pdk/contains the locked PDK setup helpers and managed PDK checkouts.smoke/syn/contains Yosys synthesis and source-export integration.smoke/sta/contains OpenSTA constraints and timing integration.librelane/contains the open-source IHP130 implementation flows, organized per product line:librelane/mini/(core hardening and full-chip pad ring) andlibrelane/tiny/(Tiny full-chip pad ring).ecc/contains the open-source ICS55 padless-core hardening flow backed by the locked ECOS Chip Compiler release.commercial/contains licensed-tool orchestration and flow logic. PDKs, foundry decks, commercial libraries, site configuration, and results remain outside Git.sdf/, when supplied by an implementation flow, contains post-layout netlist and SDF collateral consumed by post-layout simulation.
The local Makefile is reserved for implementation flows that require the selected PDK, technology collateral, and often site-specific tools.
Generated layout, report, and database outputs must remain outside tracked source paths. Treat PDK-dependent physical-design results as toolchain-specific evidence and record the selected profile, PDK, and validation command when handing off a change. See Engineering Workflow.