maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
1.3 KiB
LibreLane IHP130 Flows
This directory groups the open-source LibreLane/IHP130 implementation flows by product line:
mini/hardens the Mini SoC deliverables (retrosoc_corepadless macro and the bare-dieretrosoc_asicpad-ring chip) forSOC=MINIprofiles such asconfigs/ci/ihp130.mk.tiny/implements the bare-die Tiny MCU (retrosoc_tiny_asic, pad-ring chip only) forSOC=TINYwithconfigs/ci/ihp130-tiny.mk.bondpad/holds the shared 70 um bondpad LEF collateral used by both chip flows.
The top-level Makefile includes mini/Makefile or tiny/Makefile according
to SOC, so the target names (librelane-doctor, librelane-chip,
librelane-package, and the Mini-only librelane-core) are uniform across
product lines.
Both lines require the LibreLane 3.0.5 development environment, the locked
IHP-Open-PDK checkout under physical/pdk/, and the locked OpenSTA 3.0.0.
PDK=GF180, PDK=SKY130, and PDK=ICS55 are intentionally rejected until
their technology-specific LibreLane adapters, pad cells, macro collateral, and
signoff decks are qualified.
A successful open-source run is evidence for implementation development, not a foundry production-signoff claim. Release review still requires qualified foundry decks, package and bond planning, electrical/ESD review, and approved waivers.