mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
306 lines
11 KiB
Python
Executable File
306 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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"""Generate the IHP130 LibreLane Chip configuration from canonical SoC data."""
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from __future__ import annotations
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import argparse
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import json
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import os
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import re
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[4]
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sys.path.insert(0, str(ROOT))
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from scripts.rtl.generate_pin_map import ( # noqa: E402
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IHP130_POWER_PAD_COUNTS,
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Pad,
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ihp130_pad_instance,
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read_map,
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)
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from scripts.setup_helpers import atomic_write # noqa: E402
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SIDE_ORDER = ("south", "east", "north", "west")
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EXPECTED_SIGNAL_PADS = 112
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CLOCK_PORTS = (
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"extclk_i_pad",
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"ref24clk_i_pad",
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"audclk_i_pad",
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"jtag_tck_i_pad",
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"gpio_10_io_pad",
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"usb2_ulpi_clk_i_pad",
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)
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SRAM_INSTANCES = {
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"RM_IHPSG13_1P_4096x16_c3_bm_bist": {
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"u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store."
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"u_packet_ram.u_packet_ram.u_data_high": ([500, 500], "N"),
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"u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store."
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"u_packet_ram.u_packet_ram.u_data_low": ([1000, 500], "N"),
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},
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"RM_IHPSG13_1P_4096x8_c3_bm_bist": {
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"u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store."
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"u_packet_ram.u_packet_ram.u_ecc": ([1500, 500], "N"),
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},
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}
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def onchip_sram_instances(capacity_kib: int) -> dict[str, tuple[list[int], str]]:
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if capacity_kib <= 0 or capacity_kib % 4 != 0:
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raise ValueError("SRAM_SIZE_KIB must be a positive multiple of 4")
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count = 2 * ((capacity_kib + 7) // 8)
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return {
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"u_retrosoc.u_onchip_ram.gen_memory64."
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f"gen_bank[{index // 2}].u_ram_{'lo' if index % 2 == 0 else 'hi'}.u_mem": (
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[2000 + (index % 4) * 500, 500 + (index // 4) * 750],
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"N",
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)
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for index in range(count)
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}
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def config_path(path: Path, base: Path) -> str:
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return f"dir::{os.path.relpath(path.resolve(), base.resolve())}"
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def signal_side(pad: Pad) -> str:
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name = pad.name
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if name.startswith("sdram_"):
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return "west"
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if name.startswith("gpio_"):
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return "east"
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if name.startswith(("sdio1_", "usb2_", "xpi_")):
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return "north"
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return "south"
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def power_instances(side_index: int) -> list[str]:
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result: list[str] = []
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for local_index in range(6):
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for kind in ("vdd", "vss"):
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index = (side_index * 6) + local_index
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result.append(f"{kind}_pads[{index}].{kind}_pad")
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if local_index < 4:
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for kind in ("iovdd", "iovss"):
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index = (side_index * 4) + local_index
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result.append(f"{kind}_pads[{index}].{kind}_pad")
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return result
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def interleave(signals: list[str], supplies: list[str]) -> list[str]:
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result: list[str] = []
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signal_index = 0
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for supply_index, supply in enumerate(supplies):
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target = round(((supply_index + 1) * len(signals)) / (len(supplies) + 1))
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result.extend(signals[signal_index:target])
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signal_index = target
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result.append(supply)
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result.extend(signals[signal_index:])
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return result
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def macro_config(
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master: str, instances: dict[str, tuple[list[int], str]], header: str
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) -> dict[str, object]:
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base = "pdk_dir::libs.ref/sg13g2_sram"
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return {
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"gds": [f"{base}/gds/{master}.gds"],
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"lef": [f"{base}/lef/{master}.lef"],
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"vh": [header],
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"spice": [f"{base}/cdl/{master}.cdl"],
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"lib": {
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"*_typ_1p20V_25C": [f"{base}/lib/{master}_typ_1p20V_25C.lib"],
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"*_fast_1p32V_m40C": [f"{base}/lib/{master}_fast_1p32V_m55C.lib"],
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"*_slow_1p08V_125C": [f"{base}/lib/{master}_slow_1p08V_125C.lib"],
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},
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"instances": {
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name: {"location": location, "orientation": orientation}
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for name, (location, orientation) in instances.items()
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},
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}
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def build_config(args: argparse.Namespace) -> dict[str, object]:
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target = getattr(args, "target", "chip")
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if target not in {"chip", "core"}:
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raise ValueError("target must be chip or core")
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pads, _ = read_map(args.pin_map)
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active_pads = [pad for pad in pads if pad.feature is None or args.have_pll]
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signal_instances: dict[str, list[str]] = {side: [] for side in SIDE_ORDER}
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for pad in active_pads:
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instance = ihp130_pad_instance(pad)
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if instance is None:
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if pad.kind == "xtal" and not pad.bind:
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continue
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raise ValueError(f"IHP130 physical PAD mapping is missing for {pad.name}")
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signal_instances[signal_side(pad)].append(instance)
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flattened = [item for side in SIDE_ORDER for item in signal_instances[side]]
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if not args.have_pll and len(flattened) != EXPECTED_SIGNAL_PADS:
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raise ValueError(
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f"expected {EXPECTED_SIGNAL_PADS} signal PADs without PLL, got {len(flattened)}"
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)
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if len(flattened) != len(set(flattened)):
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raise ValueError("physical signal PAD instances are not unique")
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pad_sides = {
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side.upper(): interleave(signal_instances[side], power_instances(index))
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for index, side in enumerate(SIDE_ORDER)
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}
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all_placed = [item for side in SIDE_ORDER for item in pad_sides[side.upper()]]
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expected_total = len(flattened) + sum(IHP130_POWER_PAD_COUNTS.values())
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if len(all_placed) != expected_total or len(all_placed) != len(set(all_placed)):
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raise ValueError(
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"PAD ring placement does not cover every signal and power PAD exactly once"
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)
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config_dir = args.output.resolve().parent
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sram_header = config_path(args.sram_vh, config_dir)
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active_sram_instances = dict(SRAM_INSTANCES)
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if getattr(args, "have_sram_macro", False):
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active_sram_instances["RM_IHPSG13_1P_1024x32_c2_bm_bist"] = onchip_sram_instances(
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getattr(args, "sram_size_kib", 32)
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)
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macros = {
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master: macro_config(master, instances, sram_header)
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for master, instances in active_sram_instances.items()
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}
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macro_hooks: list[str] = []
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for instances in active_sram_instances.values():
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for instance in instances:
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bracket_start = instance.find("[")
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if bracket_start >= 0:
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bracket_end = instance.index("]", bracket_start)
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instance_pattern = (
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re.escape(instance[:bracket_start])
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+ ".*"
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+ instance[bracket_start + 1 : bracket_end]
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+ ".*"
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+ re.escape(instance[bracket_end + 1 :])
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)
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else:
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instance_pattern = re.escape(instance)
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macro_hooks.extend(
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[
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f"{instance_pattern} VDD VSS VDDARRAY! VSS!",
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f"{instance_pattern} VDD VSS VDD! VSS!",
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]
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)
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common = {
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"VERILOG_FILES": [config_path(args.rtl, config_dir)],
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"USE_SLANG": True,
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"SLANG_ARGUMENTS": ["--keep-hierarchy"],
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"VERILOG_POWER_DEFINE": None,
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"SYNTH_SHARE_RESOURCES": False,
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"SYNTH_HIERARCHY_MODE": "deferred_flatten",
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"YOSYS_LOG_LEVEL": "WARNING",
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"SYNTH_STRATEGY": "AREA 3",
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"RUN_POST_GPL_DESIGN_REPAIR": False,
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"RUN_CTS": False,
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"RUN_POST_CTS_RESIZER_TIMING": False,
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"EXTRA_EXCLUDED_CELLS": ["sg13g2_IOPad*"],
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"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
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"PNR_SDC_FILE": config_path(args.sdc, config_dir),
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"SIGNOFF_SDC_FILE": config_path(args.sdc, config_dir),
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"FALLBACK_SDC": config_path(args.sdc, config_dir),
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"STA_EXTRA_CORNER_TCL_FILE": config_path(
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ROOT / "physical/librelane/mini/sta_report_limit.tcl", config_dir
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),
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"CLOCK_PORT": list(CLOCK_PORTS),
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"CLOCK_PERIOD": 1_000_000_000 / args.ext_clk_hz,
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"VDD_NETS": ["VDD"],
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"GND_NETS": ["VSS"],
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"FP_SIZING": "absolute",
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"PDN_CORE_RING": True,
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"PDN_CORE_RING_VWIDTH": 15,
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"PDN_CORE_RING_HWIDTH": 15,
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"PDN_CORE_RING_VSPACING": 5,
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"PDN_CORE_RING_HSPACING": 5,
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"PDN_ENABLE_PINS": True,
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"ERROR_ON_PDN_VIOLATIONS": True,
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"PDN_CFG": config_path(args.pdn, config_dir),
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"MACROS": macros,
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"PDN_MACRO_CONNECTIONS": macro_hooks,
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"MAGIC_GDS_FLATGLOB": [
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"lvsres_*",
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"VIA_M1_*",
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"VIA_M2_*",
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"*_CELL_CORNER",
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"RSC_*",
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"*_CELL_SUB",
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],
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}
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if target == "core":
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return {
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"meta": {"version": 3, "flow": "Classic"},
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"DESIGN_NAME": "retrosoc_core",
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"DIE_AREA": [0, 0, 6000, 6000],
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"CORE_AREA": [120, 120, 5880, 5880],
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"PL_TARGET_DENSITY_PCT": 45,
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"PDN_CORE_RING_CONNECT_TO_PADS": False,
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**common,
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}
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return {
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"meta": {"version": 3, "flow": "Chip"},
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"DESIGN_NAME": "retrosoc_asic",
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"SYNTH_KEEP_HIERARCHY_MODULES": [
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"sg13g2_IOPadVdd",
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"sg13g2_IOPadVss",
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"sg13g2_IOPadIOVdd",
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"sg13g2_IOPadIOVss",
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],
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"PAD_SOUTH": pad_sides["SOUTH"],
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"PAD_EAST": pad_sides["EAST"],
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"PAD_NORTH": pad_sides["NORTH"],
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"PAD_WEST": pad_sides["WEST"],
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"DIE_AREA": [0, 0, 8000, 8000],
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"CORE_AREA": [365, 365, 7635, 7635],
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"PL_TARGET_DENSITY_PCT": 45,
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"PDN_CORE_RING_CONNECT_TO_PADS": True,
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"PAD_CFG": config_path(ROOT / "physical/librelane/mini/pad_cfg.tcl", config_dir),
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"PAD_BONDPAD_NAME": "bondpad_70x70",
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"EXTRA_GDS": [config_path(args.bondpad_gds, config_dir)],
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"EXTRA_LEFS": [config_path(args.bondpad_lef, config_dir)],
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"IGNORE_DISCONNECTED_MODULES": ["bondpad_70x70"],
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"MAGIC_EXT_UNIQUE": "notopports",
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**common,
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}
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def positive_integer(value: str) -> int:
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parsed = int(value)
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if parsed <= 0:
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raise argparse.ArgumentTypeError("value must be positive")
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return parsed
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--pin-map", type=Path, required=True)
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parser.add_argument("--rtl", type=Path, required=True)
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parser.add_argument("--sdc", type=Path, required=True)
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parser.add_argument("--pdn", type=Path, required=True)
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parser.add_argument("--bondpad-gds", type=Path, required=True)
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parser.add_argument("--bondpad-lef", type=Path, required=True)
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parser.add_argument("--sram-vh", type=Path, required=True)
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parser.add_argument("--ext-clk-hz", type=positive_integer, required=True)
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parser.add_argument("--aud-clk-hz", type=positive_integer, required=True)
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parser.add_argument("--have-pll", action="store_true")
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parser.add_argument("--have-sram-macro", action="store_true")
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parser.add_argument("--sram-size-kib", type=positive_integer, default=32)
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parser.add_argument("--target", choices=("chip", "core"), default="chip")
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parser.add_argument("--output", type=Path, required=True)
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args = parser.parse_args()
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try:
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config = build_config(args)
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atomic_write(args.output, json.dumps(config, indent=2, sort_keys=True) + "\n")
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except (OSError, ValueError, json.JSONDecodeError) as error:
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parser.error(str(error))
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return 0
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if __name__ == "__main__":
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raise SystemExit(main())
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