mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
71 lines
2.0 KiB
Systemverilog
71 lines
2.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
|
// SPDX-License-Identifier: MulanPSL-2.0
|
|
// Synthesis-only headers for locked IHP SRAM macro physical views.
|
|
|
|
(* blackbox *)
|
|
module RM_IHPSG13_1P_4096x16_c3_bm_bist (
|
|
input wire A_CLK,
|
|
input wire A_MEN,
|
|
input wire A_WEN,
|
|
input wire A_REN,
|
|
input wire [11:0] A_ADDR,
|
|
input wire [15:0] A_DIN,
|
|
input wire A_DLY,
|
|
output wire [15:0] A_DOUT,
|
|
input wire [15:0] A_BM,
|
|
input wire A_BIST_CLK,
|
|
input wire A_BIST_EN,
|
|
input wire A_BIST_MEN,
|
|
input wire A_BIST_WEN,
|
|
input wire A_BIST_REN,
|
|
input wire [11:0] A_BIST_ADDR,
|
|
input wire [15:0] A_BIST_DIN,
|
|
input wire [15:0] A_BIST_BM
|
|
);
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module RM_IHPSG13_1P_4096x8_c3_bm_bist (
|
|
input wire A_CLK,
|
|
input wire A_MEN,
|
|
input wire A_WEN,
|
|
input wire A_REN,
|
|
input wire [11:0] A_ADDR,
|
|
input wire [ 7:0] A_DIN,
|
|
input wire A_DLY,
|
|
output wire [ 7:0] A_DOUT,
|
|
input wire [ 7:0] A_BM,
|
|
input wire A_BIST_CLK,
|
|
input wire A_BIST_EN,
|
|
input wire A_BIST_MEN,
|
|
input wire A_BIST_WEN,
|
|
input wire A_BIST_REN,
|
|
input wire [11:0] A_BIST_ADDR,
|
|
input wire [ 7:0] A_BIST_DIN,
|
|
input wire [ 7:0] A_BIST_BM
|
|
);
|
|
endmodule
|
|
|
|
|
|
(* blackbox *)
|
|
module RM_IHPSG13_1P_1024x32_c2_bm_bist (
|
|
input wire A_CLK,
|
|
input wire A_MEN,
|
|
input wire A_WEN,
|
|
input wire A_REN,
|
|
input wire [ 9:0] A_ADDR,
|
|
input wire [31:0] A_DIN,
|
|
input wire A_DLY,
|
|
output wire [31:0] A_DOUT,
|
|
input wire [31:0] A_BM,
|
|
input wire A_BIST_CLK,
|
|
input wire A_BIST_EN,
|
|
input wire A_BIST_MEN,
|
|
input wire A_BIST_WEN,
|
|
input wire A_BIST_REN,
|
|
input wire [ 9:0] A_BIST_ADDR,
|
|
input wire [31:0] A_BIST_DIN,
|
|
input wire [31:0] A_BIST_BM
|
|
);
|
|
endmodule
|