mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
134 lines
6.6 KiB
Makefile
134 lines
6.6 KiB
Makefile
LIBRELANE_FLOW_ROOT := $(ROOT_PATH)/physical/librelane/tiny
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LIBRELANE_RUN_ROOT := $(VARIANT_ROOT)/physical/librelane/tiny/chip
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LIBRELANE_INPUT_DIR := $(LIBRELANE_RUN_ROOT)/input
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LIBRELANE_RTL := $(LIBRELANE_INPUT_DIR)/retrosoc_tiny_asic_sources.sv
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LIBRELANE_SDC := $(LIBRELANE_INPUT_DIR)/retrosoc_tiny_chip.sdc
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LIBRELANE_BONDPAD_GDS := $(LIBRELANE_INPUT_DIR)/bondpad_70x70.gds
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LIBRELANE_BONDPAD_LEF := $(ROOT_PATH)/physical/librelane/bondpad/bondpad_70x70.lef
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LIBRELANE_CONFIG := $(LIBRELANE_RUN_ROOT)/config.json
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LIBRELANE_LOG := $(LIBRELANE_RUN_ROOT)/librelane.log
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LIBRELANE_RESULT := $(LIBRELANE_RUN_ROOT)/result.json
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LIBRELANE_META_RESULT := $(META_DIR)/librelane-chip.json
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LIBRELANE_DOCTOR_RESULT := $(META_DIR)/librelane-chip-doctor.json
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LIBRELANE_FINAL_DIR := $(LIBRELANE_RUN_ROOT)/final
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LIBRELANE_ARCHIVE := $(LIBRELANE_RUN_ROOT)/retrosoc-tiny-ihp130-chip.tar.gz
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LIBRELANE_RUN_TAG ?= current
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LIBRELANE_PDK_ROOT := $(ROOT_PATH)/physical/pdk/IHP-Open-PDK
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LIBRELANE_PDK := ihp-sg13g2
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LIBRELANE_SCL := sg13g2_stdcell
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LIBRELANE_PAD := sg13g2_io
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LIBRELANE_KLAYOUT_PATH := $(LIBRELANE_PDK_ROOT)/$(LIBRELANE_PDK)/libs.tech/klayout
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LIBRELANE_BONDPAD_SCRIPT := $(LIBRELANE_PDK_ROOT)/$(LIBRELANE_PDK)/libs.tech/klayout/tech/scripts/bondpad.py
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LIBRELANE_PDN := $(LIBRELANE_FLOW_ROOT)/pdn_cfg.tcl
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LIBRELANE_SRAM_VH := $(LIBRELANE_FLOW_ROOT)/sram_blackboxes.vh
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LIBRELANE_STA_REPORT_LIMIT := $(LIBRELANE_FLOW_ROOT)/sta_report_limit.tcl
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LIBRELANE_CLOCK_DOMAINS := $(RTL_PATH)/integration/clock_reset_domains.json
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LIBRELANE_PIN_MAP := $(RTL_PATH)/pin_map/pin_map.json
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LIBRELANE_TRACKED_RTL := $(shell git -C $(ROOT_PATH) ls-files \
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'rtl/**/*.sv' 'rtl/**/*.svh' 'rtl/**/*.v' 'rtl/**/*.vh')
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LIBRELANE_SOURCE_PYTHON ?= /usr/bin/python3
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LIBRELANE_PYTHON ?= python3
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LIBRELANE_COMMAND := $(LIBRELANE_PYTHON) -m librelane
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# LibreLane 3.0.5 writes 1000 expanded paths per group at every mid-PnR STA.
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# Final multi-corner RCX STA remains mandatory; skip only the redundant reports.
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LIBRELANE_MID_PNR_SKIP ?= --skip OpenROAD.STAMidPNR
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ifneq ($(filter librelane-input librelane-doctor librelane-chip \
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librelane-openroad librelane-klayout librelane-package,$(MAKECMDGOALS)),)
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FLOW_PYTHON := $(LIBRELANE_SOURCE_PYTHON)
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endif
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LIBRELANE_FEATURE_ARGS := \
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$(if $(filter YES,$(HAVE_PLL)),--have-pll) \
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$(if $(filter YES,$(HAVE_SRAM_IF)),--have-sram-if) \
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$(if $(filter YES,$(HAVE_SRAM_MACRO)),--have-sram-macro) \
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$(if $(filter YES,$(HAVE_SVA)),--have-sva)
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LIBRELANE_CONFIG_DEPS := $(LIBRELANE_RTL) $(LIBRELANE_SDC) \
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$(LIBRELANE_PDN) $(LIBRELANE_SRAM_VH) \
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$(LIBRELANE_STA_REPORT_LIMIT) $(LIBRELANE_BONDPAD_GDS) $(LIBRELANE_BONDPAD_LEF) \
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$(LIBRELANE_FLOW_ROOT)/scripts/generate_chip_config.py
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.PHONY: librelane-check-pdk librelane-input librelane-doctor librelane-chip \
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librelane-openroad librelane-klayout librelane-package
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librelane-check-pdk:
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@test '$(PDK)' = IHP130 || { \
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echo 'physical/librelane/tiny currently implements only PDK=IHP130' >&2; exit 2; }
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@test '$(HAVE_PLL)' = NO || { \
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echo 'the IHP130 LibreLane flow has no qualified crystal PAD' >&2; exit 2; }
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$(LIBRELANE_RTL): $(FILELIST_STAMP) $(LIBRELANE_TRACKED_RTL) \
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$(ROOT_PATH)/physical/smoke/syn/tools/export_soc_sources.py | librelane-check-pdk
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@mkdir -p $(@D)
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$(FLOW_PYTHON) $(ROOT_PATH)/physical/smoke/syn/tools/export_soc_sources.py sv \
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--output-dir $(@D) --soc TINY --pdk IHP130 --simu $(SIMU) \
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--jtag-idcode $(JTAG_IDCODE) \
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--ext-clk-hz $(EXT_CLK_HZ) --aud-clk-hz $(AUD_CLK_HZ) \
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--clint-timebase-hz $(CLINT_TIMEBASE_HZ) \
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--source-filelist-dir $(GENERATED_FL_DIR) \
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--librelane-safe \
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$(LIBRELANE_FEATURE_ARGS)
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$(LIBRELANE_SDC): $(LIBRELANE_FLOW_ROOT)/scripts/generate_sdc.py \
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$(LIBRELANE_CLOCK_DOMAINS) $(LIBRELANE_PIN_MAP) | librelane-check-pdk
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@mkdir -p $(@D)
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$(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/generate_sdc.py \
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--domains $(LIBRELANE_CLOCK_DOMAINS) --pin-map $(LIBRELANE_PIN_MAP) \
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--ext-clk-hz $(EXT_CLK_HZ) --output $@
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$(LIBRELANE_BONDPAD_GDS): $(LIBRELANE_BONDPAD_SCRIPT) | librelane-check-pdk
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@mkdir -p $(@D)
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KLAYOUT_PATH=$(LIBRELANE_KLAYOUT_PATH) klayout -n sg13g2 -zz \
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-r $(LIBRELANE_BONDPAD_SCRIPT) -rd diameter=70.0 -rd shape=square \
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-rd output=$@
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@test -s $@
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$(LIBRELANE_CONFIG): $(LIBRELANE_CONFIG_DEPS)
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$(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/generate_chip_config.py \
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--pin-map $(LIBRELANE_PIN_MAP) --rtl $(LIBRELANE_RTL) --sdc $(LIBRELANE_SDC) \
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--pdn $(LIBRELANE_PDN) --bondpad-gds $(LIBRELANE_BONDPAD_GDS) \
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--bondpad-lef $(LIBRELANE_BONDPAD_LEF) --sram-vh $(LIBRELANE_SRAM_VH) \
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--ext-clk-hz $(EXT_CLK_HZ) --sram-size-kib $(SRAM_SIZE_KIB) \
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$(if $(filter YES,$(HAVE_SRAM_MACRO)),--have-sram-macro) \
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--output $@
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librelane-input: $(LIBRELANE_CONFIG)
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$(LIBRELANE_DOCTOR_RESULT): $(LIBRELANE_CONFIG) \
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$(LIBRELANE_FLOW_ROOT)/scripts/doctor.py
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@mkdir -p $(@D)
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$(LIBRELANE_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/doctor.py \
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--root $(ROOT_PATH) --config $(LIBRELANE_CONFIG) --lock $(LOCK_FILE) \
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--pin-map $(LIBRELANE_PIN_MAP) --pdk-root $(LIBRELANE_PDK_ROOT) --output $@
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librelane-doctor: $(LIBRELANE_DOCTOR_RESULT)
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librelane-chip: librelane-doctor manifest
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$(FLOW_PYTHON) $(ROOT_PATH)/scripts/run_flow.py --tool librelane \
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--log $(LIBRELANE_LOG) --result $(LIBRELANE_RESULT) --cwd $(LIBRELANE_RUN_ROOT) -- \
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$(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk --pdk $(LIBRELANE_PDK) \
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--pdk-root $(LIBRELANE_PDK_ROOT) --scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \
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--run-tag $(LIBRELANE_RUN_TAG) --overwrite --jobs $(JOBS) $(LIBRELANE_MID_PNR_SKIP) \
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--condensed --hide-progress-bar --save-views-to $(LIBRELANE_FINAL_DIR)
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@mkdir -p $(META_DIR)
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@cp $(LIBRELANE_RESULT) $(LIBRELANE_META_RESULT)
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librelane-openroad: librelane-doctor
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cd $(LIBRELANE_RUN_ROOT) && $(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk \
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--pdk $(LIBRELANE_PDK) --pdk-root $(LIBRELANE_PDK_ROOT) \
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--scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \
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--run-tag $(LIBRELANE_RUN_TAG) --last-run --flow OpenInOpenROAD
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librelane-klayout: librelane-doctor
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cd $(LIBRELANE_RUN_ROOT) && $(LIBRELANE_COMMAND) $(LIBRELANE_CONFIG) --manual-pdk \
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--pdk $(LIBRELANE_PDK) --pdk-root $(LIBRELANE_PDK_ROOT) \
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--scl $(LIBRELANE_SCL) --pad $(LIBRELANE_PAD) \
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--run-tag $(LIBRELANE_RUN_TAG) --last-run --flow OpenInKLayout
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librelane-package: librelane-chip
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$(FLOW_PYTHON) $(LIBRELANE_FLOW_ROOT)/scripts/package.py \
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--root $(ROOT_PATH) --variant-root $(VARIANT_ROOT) \
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--run-root $(LIBRELANE_RUN_ROOT) --output $(LIBRELANE_ARCHIVE)
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