mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
18 lines
655 B
Tcl
18 lines
655 B
Tcl
# IHP SG13G2 supply pads are physical-only cells and are not retained by Yosys.
|
|
# Tiny ships two core and two IO supply pairs per pad-ring side (8/8/8/8).
|
|
foreach {kind master count} {
|
|
vdd sg13g2_IOPadVdd 8
|
|
vss sg13g2_IOPadVss 8
|
|
iovdd sg13g2_IOPadIOVdd 8
|
|
iovss sg13g2_IOPadIOVss 8
|
|
} {
|
|
for {set index 0} {$index < $count} {incr index} {
|
|
set instance_name [format {%s_pads[%d].%s_pad} $kind $index $kind]
|
|
set db_block [ord::get_db_block]
|
|
if {[$db_block findInst $instance_name] == "NULL"} {
|
|
make_instance $instance_name $master
|
|
}
|
|
}
|
|
}
|
|
source $::env(SCRIPTS_DIR)/openroad/common/pad_cfg.tcl
|