mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
296 lines
11 KiB
Python
296 lines
11 KiB
Python
#!/usr/bin/env python3
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"""Generate the IHP130 LibreLane Chip configuration for the Tiny SoC."""
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from __future__ import annotations
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import argparse
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import json
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import os
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import re
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[4]
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sys.path.insert(0, str(ROOT))
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from scripts.rtl.generate_pin_map import ( # noqa: E402
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POWER_PAD_KINDS,
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Pad,
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ihp130_pad_instance,
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read_map,
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read_power_pad_counts,
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)
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from scripts.setup_helpers import atomic_write # noqa: E402
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SIDE_ORDER = ("south", "east", "north", "west")
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EXPECTED_SIGNAL_PADS = 52
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CLOCK_PORTS = ("extclk_i_pad", "jtag_tck_i_pad")
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SRAM_MASTER = "RM_IHPSG13_1P_1024x32_c2_bm_bist"
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SRAM_INSTANCE = "u_soc.u_sram.gen_memory.gen_bank[{index}].u_ram.u_mem"
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SRAM_COLUMNS = 8
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SRAM_ORIGIN = (400, 600)
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# Detailed routing requires an M2 track inside each bank's 0.26 um bottom-edge
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# pin stubs: the bank y origin must keep residue {0, 0.24} mod 0.42 um (the M2
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# vertical track pitch); a y pitch of 504 um (1200 x 0.42) preserves it per row.
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SRAM_PITCH = (480, 504)
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DIE_AREA = [0, 0, 4700, 4700]
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CORE_AREA = [365, 365, 4335, 4335]
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def config_path(path: Path, base: Path) -> str:
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return f"dir::{os.path.relpath(path.resolve(), base.resolve())}"
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def signal_side(pad: Pad) -> str:
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name = pad.name
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if name.startswith("gpio_"):
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return "east" if pad.index is not None and pad.index < 16 else "west"
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if name.startswith("xpi_"):
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return "north"
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return "south"
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def power_instances(counts: dict[str, int], side_index: int) -> list[str]:
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per_side: dict[str, int] = {}
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for kind in POWER_PAD_KINDS:
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count = counts[kind]
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if count % len(SIDE_ORDER) != 0:
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raise ValueError(
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f"power_pads.{kind}={count} cannot be distributed across "
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f"{len(SIDE_ORDER)} pad-ring sides"
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)
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per_side[kind] = count // len(SIDE_ORDER)
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result: list[str] = []
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for local_index in range(per_side["vdd"]):
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for kind in ("vdd", "vss"):
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index = (side_index * per_side[kind]) + local_index
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result.append(f"{kind}_pads[{index}].{kind}_pad")
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for local_index in range(per_side["iovdd"]):
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for kind in ("iovdd", "iovss"):
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index = (side_index * per_side[kind]) + local_index
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result.append(f"{kind}_pads[{index}].{kind}_pad")
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return result
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def interleave(signals: list[str], supplies: list[str]) -> list[str]:
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result: list[str] = []
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signal_index = 0
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for supply_index, supply in enumerate(supplies):
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target = round(((supply_index + 1) * len(signals)) / (len(supplies) + 1))
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result.extend(signals[signal_index:target])
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signal_index = target
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result.append(supply)
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result.extend(signals[signal_index:])
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return result
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def sram_instances(capacity_kib: int) -> dict[str, tuple[list[int], str]]:
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if capacity_kib <= 0 or capacity_kib % 4 != 0:
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raise ValueError("SRAM_SIZE_KIB must be a positive multiple of 4")
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instances: dict[str, tuple[list[int], str]] = {}
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for index in range(capacity_kib // 4):
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column, row = index % SRAM_COLUMNS, index // SRAM_COLUMNS
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location = [
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SRAM_ORIGIN[0] + column * SRAM_PITCH[0],
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SRAM_ORIGIN[1] + row * SRAM_PITCH[1],
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]
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instances[SRAM_INSTANCE.format(index=index)] = (location, "N")
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return instances
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def macro_config(instances: dict[str, tuple[list[int], str]], header: str) -> dict[str, object]:
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base = "pdk_dir::libs.ref/sg13g2_sram"
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master = SRAM_MASTER
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return {
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"gds": [f"{base}/gds/{master}.gds"],
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"lef": [f"{base}/lef/{master}.lef"],
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"vh": [header],
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"spice": [f"{base}/cdl/{master}.cdl"],
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"lib": {
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"*_typ_1p20V_25C": [f"{base}/lib/{master}_typ_1p20V_25C.lib"],
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"*_fast_1p32V_m40C": [f"{base}/lib/{master}_fast_1p32V_m55C.lib"],
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"*_slow_1p08V_125C": [f"{base}/lib/{master}_slow_1p08V_125C.lib"],
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},
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"instances": {
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name: {"location": location, "orientation": orientation}
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for name, (location, orientation) in instances.items()
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},
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}
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def macro_hooks(instances: dict[str, tuple[list[int], str]]) -> list[str]:
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hooks: list[str] = []
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for instance in instances:
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bracket_start = instance.find("[")
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if bracket_start >= 0:
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bracket_end = instance.index("]", bracket_start)
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instance_pattern = (
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re.escape(instance[:bracket_start])
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+ ".*"
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+ instance[bracket_start + 1 : bracket_end]
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+ ".*"
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+ re.escape(instance[bracket_end + 1 :])
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)
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else:
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instance_pattern = re.escape(instance)
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hooks.extend(
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[
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f"{instance_pattern} VDD VSS VDDARRAY! VSS!",
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f"{instance_pattern} VDD VSS VDD! VSS!",
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]
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)
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return hooks
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def build_config(args: argparse.Namespace) -> dict[str, object]:
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pads, _ = read_map(args.pin_map)
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power_counts = read_power_pad_counts(args.pin_map)
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signal_instances: dict[str, list[str]] = {side: [] for side in SIDE_ORDER}
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for pad in pads:
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instance = ihp130_pad_instance(pad)
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if instance is None:
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raise ValueError(f"IHP130 physical PAD mapping is missing for {pad.name}")
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signal_instances[signal_side(pad)].append(instance)
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flattened = [item for side in SIDE_ORDER for item in signal_instances[side]]
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if len(flattened) != EXPECTED_SIGNAL_PADS:
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raise ValueError(
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f"expected {EXPECTED_SIGNAL_PADS} signal PADs, got {len(flattened)}"
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)
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if len(flattened) != len(set(flattened)):
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raise ValueError("physical signal PAD instances are not unique")
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pad_sides = {
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side.upper(): interleave(signal_instances[side], power_instances(power_counts, index))
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for index, side in enumerate(SIDE_ORDER)
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}
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all_placed = [item for side in SIDE_ORDER for item in pad_sides[side.upper()]]
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expected_total = len(flattened) + sum(power_counts.values())
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if len(all_placed) != expected_total or len(all_placed) != len(set(all_placed)):
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raise ValueError(
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"PAD ring placement does not cover every signal and power PAD exactly once"
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)
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config_dir = args.output.resolve().parent
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sram_header = config_path(args.sram_vh, config_dir)
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active_sram_instances = sram_instances(args.sram_size_kib) if args.have_sram_macro else {}
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macros = (
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{SRAM_MASTER: macro_config(active_sram_instances, sram_header)}
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if active_sram_instances
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else {}
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)
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return {
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"meta": {"version": 3, "flow": "Chip"},
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"DESIGN_NAME": "retrosoc_tiny_asic",
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"VERILOG_FILES": [config_path(args.rtl, config_dir)],
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"USE_SLANG": True,
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"SLANG_ARGUMENTS": ["--keep-hierarchy"],
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"VERILOG_POWER_DEFINE": None,
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"SYNTH_SHARE_RESOURCES": False,
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"SYNTH_HIERARCHY_MODE": "deferred_flatten",
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"SYNTH_KEEP_HIERARCHY_MODULES": [
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"sg13g2_IOPadVdd",
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"sg13g2_IOPadVss",
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"sg13g2_IOPadIOVdd",
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"sg13g2_IOPadIOVss",
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],
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"YOSYS_LOG_LEVEL": "WARNING",
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"SYNTH_STRATEGY": "AREA 3",
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# Hotspots sit at the SRAM bank pin edges; detailed routing resolves the
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# moderate estimated overflow. The signoff bar remains detailed-routing
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# DRC, post-RCX multi-corner STA, KLayout DRC, and netgen LVS.
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"GRT_ALLOW_CONGESTION": True,
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# This OpenROAD build's antenna analysis leaks/stalls on the Tiny netlist
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# (check_antennas -verbose ballooned to 248 GB RSS; repair_antennas did
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# not converge in 100 minutes). Skip the report/repair steps; antenna
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# coverage is a documented gap for this flow revision.
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"RUN_ANTENNA_REPAIR": False,
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# Hazard3 with EXTENSION_A=0 (RV32IM) leaves x_amo_phase undriven by
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# design; every use is masked by a constant-false guard. Waive the
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# three benign "used but has no driver" check errors.
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"ERROR_ON_SYNTH_CHECKS": False,
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"RUN_POST_GPL_DESIGN_REPAIR": False,
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"RUN_CTS": False,
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"RUN_POST_CTS_RESIZER_TIMING": False,
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"EXTRA_EXCLUDED_CELLS": ["sg13g2_IOPad*"],
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"PRIMARY_GDSII_STREAMOUT_TOOL": "klayout",
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"PNR_SDC_FILE": config_path(args.sdc, config_dir),
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"SIGNOFF_SDC_FILE": config_path(args.sdc, config_dir),
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"FALLBACK_SDC": config_path(args.sdc, config_dir),
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"STA_EXTRA_CORNER_TCL_FILE": config_path(
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ROOT / "physical/librelane/tiny/sta_report_limit.tcl", config_dir
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),
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"CLOCK_PORT": list(CLOCK_PORTS),
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"CLOCK_PERIOD": 1_000_000_000 / args.ext_clk_hz,
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"VDD_NETS": ["VDD"],
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"GND_NETS": ["VSS"],
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"FP_SIZING": "absolute",
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"PDN_CORE_RING": True,
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"PDN_CORE_RING_VWIDTH": 15,
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"PDN_CORE_RING_HWIDTH": 15,
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"PDN_CORE_RING_VSPACING": 5,
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"PDN_CORE_RING_HSPACING": 5,
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"PDN_ENABLE_PINS": True,
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"ERROR_ON_PDN_VIOLATIONS": True,
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"PDN_CFG": config_path(args.pdn, config_dir),
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"MACROS": macros,
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"PDN_MACRO_CONNECTIONS": macro_hooks(active_sram_instances),
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"MAGIC_GDS_FLATGLOB": [
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"lvsres_*",
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"VIA_M1_*",
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"VIA_M2_*",
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"*_CELL_CORNER",
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"RSC_*",
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"*_CELL_SUB",
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],
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"PAD_SOUTH": pad_sides["SOUTH"],
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"PAD_EAST": pad_sides["EAST"],
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"PAD_NORTH": pad_sides["NORTH"],
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"PAD_WEST": pad_sides["WEST"],
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"DIE_AREA": DIE_AREA,
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"CORE_AREA": CORE_AREA,
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"PL_TARGET_DENSITY_PCT": 45,
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"PDN_CORE_RING_CONNECT_TO_PADS": True,
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"PAD_CFG": config_path(ROOT / "physical/librelane/tiny/pad_cfg.tcl", config_dir),
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"PAD_BONDPAD_NAME": "bondpad_70x70",
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"EXTRA_GDS": [config_path(args.bondpad_gds, config_dir)],
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"EXTRA_LEFS": [config_path(args.bondpad_lef, config_dir)],
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"IGNORE_DISCONNECTED_MODULES": ["bondpad_70x70"],
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"MAGIC_EXT_UNIQUE": "notopports",
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}
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def positive_integer(value: str) -> int:
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parsed = int(value)
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if parsed <= 0:
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raise argparse.ArgumentTypeError("value must be positive")
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return parsed
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def main() -> int:
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parser = argparse.ArgumentParser(description=__doc__)
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parser.add_argument("--pin-map", type=Path, required=True)
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parser.add_argument("--rtl", type=Path, required=True)
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parser.add_argument("--sdc", type=Path, required=True)
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parser.add_argument("--pdn", type=Path, required=True)
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parser.add_argument("--bondpad-gds", type=Path, required=True)
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parser.add_argument("--bondpad-lef", type=Path, required=True)
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parser.add_argument("--sram-vh", type=Path, required=True)
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parser.add_argument("--ext-clk-hz", type=positive_integer, required=True)
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parser.add_argument("--have-sram-macro", action="store_true")
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parser.add_argument("--sram-size-kib", type=positive_integer, default=128)
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parser.add_argument("--output", type=Path, required=True)
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args = parser.parse_args()
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try:
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config = build_config(args)
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atomic_write(args.output, json.dumps(config, indent=2, sort_keys=True) + "\n")
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except (OSError, ValueError, json.JSONDecodeError) as error:
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parser.error(str(error))
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return 0
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if __name__ == "__main__":
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raise SystemExit(main())
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