mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
257 lines
11 KiB
Python
257 lines
11 KiB
Python
"""Tests for IHP130 LibreLane core and pad-ring flows."""
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from __future__ import annotations
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import importlib.util
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import json
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import re
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from pathlib import Path
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from types import SimpleNamespace
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ROOT = Path(__file__).resolve().parents[1]
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PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
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DOMAINS = ROOT / "rtl/mini/integration/clock_reset_domains.json"
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FLOW_ROOT = ROOT / "physical/librelane/mini"
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def load_module(name: str, path: Path):
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spec = importlib.util.spec_from_file_location(name, path)
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assert spec is not None and spec.loader is not None
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module = importlib.util.module_from_spec(spec)
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spec.loader.exec_module(module)
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return module
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def chip_arguments(tmp_path: Path) -> SimpleNamespace:
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return SimpleNamespace(
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pin_map=PIN_MAP,
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rtl=tmp_path / "retrosoc_asic_sources.sv",
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sdc=tmp_path / "retrosoc_asic.sdc",
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pdn=FLOW_ROOT / "pdn_cfg.tcl",
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bondpad_gds=tmp_path / "bondpad_70x70.gds",
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bondpad_lef=FLOW_ROOT / "bondpad/bondpad_70x70.lef",
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sram_vh=FLOW_ROOT / "sram_blackboxes.vh",
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ext_clk_hz=72_000_000,
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aud_clk_hz=18_432_000,
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have_pll=False,
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output=tmp_path / "config.json",
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)
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def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> None:
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module = load_module("retrosoc_librelane_config", FLOW_ROOT / "scripts/generate_chip_config.py")
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config = module.build_config(chip_arguments(tmp_path))
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sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
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placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
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assert len(placed) == 192
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assert len(placed) == len(set(placed))
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assert {side: len(instances) for side, instances in sides.items()} == {
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"south": 33,
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"east": 52,
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"north": 48,
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"west": 59,
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}
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assert sum(item.startswith("vdd_pads[") for item in placed) == 24
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assert sum(item.startswith("vss_pads[") for item in placed) == 24
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assert sum(item.startswith("iovdd_pads[") for item in placed) == 16
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assert sum(item.startswith("iovss_pads[") for item in placed) == 16
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_ref24clk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_sdram_dq15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert config["DIE_AREA"] == [0, 0, 8000, 8000]
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assert config["CORE_AREA"] == [365, 365, 7635, 7635]
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assert config["PL_TARGET_DENSITY_PCT"] == 45
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assert config["USE_SLANG"] is True
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assert config["SLANG_ARGUMENTS"] == ["--keep-hierarchy"]
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assert config["VERILOG_POWER_DEFINE"] is None
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assert config["SYNTH_SHARE_RESOURCES"] is False
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assert config["SYNTH_HIERARCHY_MODE"] == "deferred_flatten"
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assert config["SYNTH_KEEP_HIERARCHY_MODULES"] == [
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"sg13g2_IOPadVdd",
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"sg13g2_IOPadVss",
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"sg13g2_IOPadIOVdd",
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"sg13g2_IOPadIOVss",
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]
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assert config["YOSYS_LOG_LEVEL"] == "WARNING"
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assert config["SYNTH_STRATEGY"] == "AREA 3"
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assert config["RUN_POST_GPL_DESIGN_REPAIR"] is False
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assert config["RUN_CTS"] is False
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assert config["RUN_POST_CTS_RESIZER_TIMING"] is False
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assert config["EXTRA_EXCLUDED_CELLS"] == ["sg13g2_IOPad*"]
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assert config["VDD_NETS"] == ["VDD"]
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assert config["GND_NETS"] == ["VSS"]
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assert config["PAD_CFG"].endswith("physical/librelane/mini/pad_cfg.tcl")
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assert config["PDN_ENABLE_PINS"] is True
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assert config["ERROR_ON_PDN_VIOLATIONS"] is True
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assert config["STA_EXTRA_CORNER_TCL_FILE"].endswith(
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"physical/librelane/mini/sta_report_limit.tcl"
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)
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assert set(config["MACROS"]) == {
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"RM_IHPSG13_1P_4096x16_c3_bm_bist",
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"RM_IHPSG13_1P_4096x8_c3_bm_bist",
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}
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assert len(config["PDN_MACRO_CONNECTIONS"]) == 6
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def test_core_config_uses_a_padless_classic_flow(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_librelane_core_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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arguments = chip_arguments(tmp_path)
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arguments.target = "core"
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config = module.build_config(arguments)
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assert config["meta"] == {"version": 3, "flow": "Classic"}
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assert config["DESIGN_NAME"] == "retrosoc_core"
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assert config["DIE_AREA"] == [0, 0, 6000, 6000]
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assert config["CORE_AREA"] == [120, 120, 5880, 5880]
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assert config["PDN_CORE_RING_CONNECT_TO_PADS"] is False
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assert "PAD_CFG" not in config
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assert not any(key.startswith("PAD_") for key in config)
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assert "PAD_BONDPAD_NAME" not in config
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assert set(config["MACROS"]) == {
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"RM_IHPSG13_1P_4096x16_c3_bm_bist",
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"RM_IHPSG13_1P_4096x8_c3_bm_bist",
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}
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def test_chip_config_includes_configured_onchip_sram_banks(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_librelane_sram_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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arguments = chip_arguments(tmp_path)
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arguments.have_sram_macro = True
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arguments.sram_size_kib = 32
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config = module.build_config(arguments)
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macro = config["MACROS"]["RM_IHPSG13_1P_1024x32_c2_bm_bist"]
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assert len(macro["instances"]) == 8
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assert (
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"u_retrosoc.u_onchip_ram.gen_memory64.gen_bank[0].u_ram_lo.u_mem"
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in macro["instances"]
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)
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assert (
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"u_retrosoc.u_onchip_ram.gen_memory64.gen_bank[3].u_ram_hi.u_mem"
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in macro["instances"]
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)
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assert any(
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"gen_bank.*0.*\\.u_ram" in connection
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for connection in config["PDN_MACRO_CONNECTIONS"]
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)
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blackboxes = (FLOW_ROOT / "sram_blackboxes.vh").read_text(encoding="utf-8")
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assert "module RM_IHPSG13_1P_1024x32_c2_bm_bist" in blackboxes
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def test_chip_sdc_is_pad_aware_and_does_not_false_path_all_io(tmp_path: Path) -> None:
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module = load_module("retrosoc_librelane_sdc", FLOW_ROOT / "scripts/generate_sdc.py")
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arguments = SimpleNamespace(
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domains=DOMAINS,
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pin_map=PIN_MAP,
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ext_clk_hz=72_000_000,
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aud_clk_hz=18_432_000,
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have_pll=False,
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)
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sdc = module.render(arguments)
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_usb2_ulpi_clk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_rcu.u_sys_clk_buf.u_sg13g2_buf_1/X" in sdc
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assert "create_generated_clock -name clk_system" in sdc
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assert "set_clock_groups -name retrosoc_async -asynchronous" in sdc
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assert "set_propagated_clock" not in sdc
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assert "set_input_delay -max" in sdc
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assert "set_output_delay -max" in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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assert "set_false_path -from [all_inputs]" not in sdc
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assert "set_false_path -to [all_outputs]" not in sdc
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def test_core_sdc_constrains_logical_top_ports(tmp_path: Path) -> None:
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module = load_module("retrosoc_librelane_core_sdc", FLOW_ROOT / "scripts/generate_sdc.py")
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arguments = SimpleNamespace(
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domains=DOMAINS,
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pin_map=PIN_MAP,
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ext_clk_hz=72_000_000,
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aud_clk_hz=18_432_000,
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have_pll=False,
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target="core",
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)
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sdc = module.render(arguments)
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assert 'require_ports "clock external" {extclk_i_pad}' in sdc
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assert 'require_ports "clock usb2_ulpi" {usb2_ulpi_clk_i_pad}' in sdc
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" not in sdc
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assert "u_rcu.u_sys_clk_buf.u_sg13g2_buf_1/X" in sdc
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def test_librelane_flow_exposes_core_and_chip_targets() -> None:
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makefile = (FLOW_ROOT / "Makefile").read_text(encoding="utf-8")
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top_makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
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lock = json.loads((ROOT / "dependencies/dependencies.lock.json").read_text())
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assert "librelane-chip:" in makefile
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assert "librelane-core:" in makefile
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assert "librelane-core-package:" in makefile
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assert re.search(r"^LIBRELANE_TARGET\s+\?=\s+chip$", makefile, flags=re.MULTILINE)
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assert "LIBRELANE_COMMAND := $(LIBRELANE_PYTHON) -m librelane" in makefile
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assert "--skip OpenROAD.STAMidPNR" in makefile
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assert "--librelane-safe" in makefile
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assert "librelane-all" not in makefile
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assert "include physical/librelane/mini/Makefile" in top_makefile
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ihp_filelist = (ROOT / "rtl/filelist/pdk_ihp130.fl").read_text(encoding="utf-8")
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assert ihp_filelist.index("sg13g2_udp.v") < ihp_filelist.index("sg13g2_stdcell.v")
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assert lock["sources"]["pdk_ihp130"]["revision"] == ("970a7688e7dcce2a6172797df9ef47bde2f60f9f")
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doctor = (FLOW_ROOT / "scripts/doctor.py").read_text(encoding="utf-8")
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assert 'EXPECTED_OPENSTA_VERSION = "3.0.0"' in doctor
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def test_bondpad_lef_matches_the_generated_master_contract() -> None:
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lef = (ROOT / "physical/librelane/bondpad/bondpad_70x70.lef").read_text(encoding="utf-8")
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assert "MACRO bondpad_70x70" in lef
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assert "CLASS COVER" in lef
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assert "SIZE 70.0 BY 70.0" in lef
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assert "SITE sg13g2_ioSite" in lef
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def test_sta_report_wrapper_caps_only_expanded_path_enumeration() -> None:
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wrapper = (FLOW_ROOT / "sta_report_limit.tcl").read_text(encoding="utf-8")
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assert "set ::retrosoc_sta_group_path_count 10" in wrapper
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assert "OpenSTA executable" in wrapper
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assert "rename report_checks ::retrosoc_report_checks" in wrapper
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assert "lsearch -exact $args -group_path_count" in wrapper
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assert "lappend args -group_path_count" in wrapper
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assert "rename report_check_types ::retrosoc_report_check_types" in wrapper
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assert "lsearch -exact $args -violators" in wrapper
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assert "rename report_parasitic_annotation" in wrapper
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assert "lsearch -exact $args -report_unannotated" in wrapper
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assert "::retrosoc_report_checks" in wrapper
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def test_pdn_connects_all_ihp_pad_power_rails() -> None:
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pdn = (FLOW_ROOT / "pdn_cfg.tcl").read_text(encoding="utf-8")
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assert "findNet $vdd" in pdn
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assert "findNet $gnd" in pdn
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assert "foreach {net signal_type} {IOVDD POWER IOVSS GROUND}" in pdn
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pad_cfg = (FLOW_ROOT / "pad_cfg.tcl").read_text(encoding="utf-8")
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assert "make_instance $instance_name $master" in pad_cfg
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assert "proc reconnect_ihp_padring_rails" in pdn
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assert "odb::dbITerm_connect $iterm $net" in pdn
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assert "set stdcell_grid_args [list]" in pdn
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assert '-pins "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"' in pdn
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assert "odb::dbTechLayer_setDirection" not in pdn
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assert "Metal4 HORIZONTAL" not in pdn
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assert '-layers "Metal2 Metal3"' in pdn
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assert "-extend_to_core_ring" in pdn
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assert "-connect_to_pad_layers TopMetal2" in pdn
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assert '-layers "Metal3 Metal4"' in pdn
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assert "-layer Metal4" in pdn
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assert "-net $::env(VDD_NET) -inst_pattern .* -pin_pattern vdd -power" in pdn
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assert "-net $::env(GND_NET) -inst_pattern .* -pin_pattern vss -ground" in pdn
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assert "-net IOVDD -inst_pattern .* -pin_pattern iovdd -power" in pdn
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assert "-net IOVSS -inst_pattern .* -pin_pattern iovss -ground" in pdn
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