mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
289 lines
11 KiB
Python
289 lines
11 KiB
Python
"""Tests for the canonical Mini SoC pin-map generator."""
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from __future__ import annotations
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import json
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import re
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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GENERATOR = ROOT / "scripts/rtl/generate_pin_map.py"
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PIN_MAP = ROOT / "rtl/mini/pin_map/pin_map.json"
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FPGA_TOP = ROOT / "fpga/mini/retrosoc_top.sv"
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FPGA_XDC = ROOT / "fpga/mini/starrysky_v2.xdc"
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def generate(output_dir: Path) -> None:
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subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--map",
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str(PIN_MAP),
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"--output-dir",
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str(output_dir),
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],
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check=True,
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)
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def validate(map_path: Path) -> subprocess.CompletedProcess[str]:
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return subprocess.run(
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[sys.executable, str(GENERATOR), "--map", str(map_path), "--check"],
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text=True,
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capture_output=True,
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)
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def test_pin_map_generates_asic_and_platform_bindings(tmp_path: Path) -> None:
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generate(tmp_path)
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ports = (tmp_path / "rtl/retrosoc_asic_ports.svh").read_text(encoding="utf-8")
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pads = (tmp_path / "rtl/retrosoc_asic_pad_bindings.svh").read_text(encoding="utf-8")
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core_ports = (tmp_path / "rtl/retrosoc_core_ports.svh").read_text(encoding="utf-8")
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core_bindings = (tmp_path / "rtl/retrosoc_core_bindings.svh").read_text(encoding="utf-8")
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fpga = (tmp_path / "rtl/retrosoc_asic_fpga_mini_bindings.svh").read_text(encoding="utf-8")
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testbench = (tmp_path / "rtl/retrosoc_asic_tb_bindings.svh").read_text(encoding="utf-8")
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verilator = (tmp_path / "rtl/retrosoc_asic_verilator_bindings.svh").read_text(encoding="utf-8")
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assert "inout wire IOVDD," in ports
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assert "inout wire IOVSS," in ports
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assert "inout wire VDD," in ports
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assert "inout wire VSS," in ports
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assert "inout wire VDD," not in core_ports
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assert "inout extclk_i_pad," in core_ports
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assert "assign s_ext_clk = extclk_i_pad;" in core_bindings
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assert "inout ref24clk_i_pad," in core_ports
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assert "assign s_ref24_clk = ref24clk_i_pad;" in core_bindings
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assert "assign gpio_0_io_pad = u_gpio_if.oe_o[0] ? u_gpio_if.do_o[0] : 1'bz;" in core_bindings
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assert "assign u_sdram_if.dq_i[15] = sdram_dq15_io_pad;" in core_bindings
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assert "inout extclk_i_pad," in ports
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assert "inout ref24clk_i_pad," in ports
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assert "inout sdram_dq15_io_pad" in ports
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assert "inout jtag_tck_i_pad" in ports
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assert "inout jtag_trst_n_i_pad" in ports
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assert "output jtag_tdo_o_pad" in ports
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assert "output sdio1_clk_o_pad," in ports
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assert "inout sdio1_cmd_io_pad," in ports
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assert "inout sdio1_dat3_io_pad," in ports
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assert "inout usb2_ulpi_clk_i_pad," in ports
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assert "inout usb2_ulpi_data7_io_pad," in ports
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assert "output usb2_ulpi_stp_o_pad," in ports
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assert "output usb2_ulpi_reset_n_o_pad," in ports
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assert "HAVE_DEBUG" not in ports
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assert "HAVE_DEBUG" not in pads
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assert "u_gpio_31_io_pad" in pads
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assert "tc_io_in_pad u_ref24clk_i_pad" in pads
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assert "u_sdram_dq15_io_pad" in pads
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assert "u_sdio1_clk_o_pad" in pads
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assert "tc_io_out_pad u_sdio1_clk_o_pad" in pads
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assert "u_sdio1_cmd_io_pad" in pads
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assert ".c2p(u_sdio1_if.cmd_do_o)" in pads
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assert ".c2p_en(u_sdio1_if.cmd_oe_o)" in pads
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assert ".p2c(u_sdio1_if.cmd_di_i)" in pads
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assert "tc_io_in_pad u_usb2_ulpi_clk_i_pad" in pads
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assert ".p2c(s_usb2_ulpi_clk)" in pads
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assert "`define RETROSOC_PAD_POWER_CONNECTIONS" in pads
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assert "sg13g2_IOPadIOVdd iovdd_pad" in pads
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assert "for (genvar i = 0; i < 24; i++) begin : vdd_pads" in pads
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assert "for (genvar i = 0; i < 24; i++) begin : vss_pads" in pads
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assert "for (genvar i = 0; i < 16; i++) begin : iovdd_pads" in pads
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assert "for (genvar i = 0; i < 16; i++) begin : iovss_pads" in pads
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assert "u_usb2_ulpi_data7_io_pad" in pads
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assert ".c2p(u_usb2_ulpi_if.data_do_o[7])" in pads
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assert ".c2p_en(u_usb2_ulpi_if.data_oe_o)" in pads
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assert ".p2c(u_usb2_ulpi_if.data_di_i[7])" in pads
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assert "tc_io_out_pad u_usb2_ulpi_stp_o_pad" in pads
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assert ".gpio_30_io_pad(gpio_io30)" in fpga
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assert ".gpio_15_io_pad()" in fpga
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assert ".gpio_24_io_pad(s_psram_dat1)" in testbench
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assert testbench.count(".gpio_24_io_pad(") == 1
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assert ".sdram_clk_o_pad(s_sdram_clk)" in verilator
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assert ".ref24clk_i_pad(s_ref24_clk)" in verilator
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assert ".sdram_dq15_io_pad(s_sdram_dq[15])" in verilator
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assert ".jtag_tck_i_pad(s_jtag_tck)" in verilator
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assert ".jtag_tdo_o_pad(s_jtag_tdo)" in verilator
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assert ".sdio1_clk_o_pad(sdio1_clk_o)" in verilator
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assert ".sdio1_cmd_io_pad(sdio1_cmd_io)" in verilator
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assert ".sdio1_dat3_io_pad(sdio1_dat3_io)" in verilator
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assert ".usb2_ulpi_clk_i_pad(s_usb2_ulpi_clk)" in verilator
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assert ".usb2_ulpi_data7_io_pad(s_usb2_ulpi_data[7])" in verilator
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assert ".sdio1_clk_o_pad(s_sdio1_clk)" in testbench
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assert ".sdio1_cmd_io_pad(s_sdio1_cmd)" in testbench
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assert ".sdio1_dat0_io_pad(s_sdio1_dat[0])" in testbench
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assert ".usb2_ulpi_clk_i_pad(s_usb2_ulpi_clk)" in testbench
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assert ".usb2_ulpi_data0_io_pad(s_usb2_ulpi_data[0])" in testbench
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assert ".sdio1_clk_o_pad()" in fpga
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assert ".sdio1_cmd_io_pad()" in fpga
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assert ".usb2_ulpi_clk_i_pad(s_usb2_ulpi_clk)" in fpga
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assert ".usb2_ulpi_data0_io_pad(s_usb2_ulpi_data[0])" in fpga
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assert ".jtag_tck_i_pad(s_jtag_tck)" in testbench
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assert "user_gpio_" not in ports
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assert "user_gpio_" not in pads
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assert "user_gpio_" not in testbench
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def test_pin_map_rejects_duplicate_pads(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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document["pads"][0]["ports"].append({"name": "extclk_i_pad", "signal": "s_duplicate_clock"})
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invalid_map = tmp_path / "duplicate.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "pad names must be unique" in result.stderr
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def test_pin_map_rejects_non_object_port_entry(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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document["pads"][0]["ports"].append("extclk_i_pad")
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invalid_map = tmp_path / "invalid-port.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "ports entries must be objects" in result.stderr
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def test_pin_map_rejects_unknown_profile_pad(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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document["profiles"]["tb"]["bindings"]["unknown_pad"] = "s_unknown"
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invalid_map = tmp_path / "unknown.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "unknown pad" in result.stderr
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def test_pin_map_requires_explicit_bidirectional_peripheral_signals(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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bidirectional_pad = next(
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pad
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for pad in document["pads"]
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if any("output_enable" in port for port in pad.get("ports", []))
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)
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bidirectional_port = next(
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port for port in bidirectional_pad["ports"] if "output_enable" in port
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)
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bidirectional_port.pop("output_enable")
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invalid_map = tmp_path / "missing-bidir-signal.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "requires input, output, and output_enable" in result.stderr
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def test_pin_map_tiny_power_pads_override(tmp_path: Path) -> None:
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subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--map",
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str(ROOT / "rtl/tiny/pin_map/pin_map.json"),
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"--output-dir",
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str(tmp_path),
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],
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check=True,
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)
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pads = (tmp_path / "rtl/retrosoc_asic_pad_bindings.svh").read_text(encoding="utf-8")
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assert "for (genvar i = 0; i < 8; i++) begin : vdd_pads" in pads
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assert "for (genvar i = 0; i < 8; i++) begin : vss_pads" in pads
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assert "for (genvar i = 0; i < 8; i++) begin : iovdd_pads" in pads
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assert "for (genvar i = 0; i < 8; i++) begin : iovss_pads" in pads
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assert "i < 24" not in pads
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assert "i < 16" not in pads
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def test_pin_map_rejects_incomplete_power_pads(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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document["power_pads"] = {"vdd": 24, "vss": 24, "iovdd": 16}
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invalid_map = tmp_path / "incomplete-power-pads.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "power_pads" in result.stderr
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def test_pin_map_rejects_non_positive_power_pads(tmp_path: Path) -> None:
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document = json.loads(PIN_MAP.read_text(encoding="utf-8"))
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document["power_pads"] = {"vdd": 0, "vss": 24, "iovdd": 16, "iovss": 16}
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invalid_map = tmp_path / "non-positive-power-pads.json"
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invalid_map.write_text(json.dumps(document), encoding="utf-8")
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result = validate(invalid_map)
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assert result.returncode != 0
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assert "power_pads.vdd" in result.stderr
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def test_fpga_constraints_reference_declared_top_ports() -> None:
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top_ports = set(
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re.findall(
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r"^\s*(?:input|output|inout)\s+([A-Za-z_][A-Za-z0-9_]*)",
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FPGA_TOP.read_text(encoding="utf-8"),
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re.MULTILINE,
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)
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)
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xdc_ports = set(
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re.findall(
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r"\[get_ports\s+([A-Za-z_][A-Za-z0-9_]*)\]", FPGA_XDC.read_text(encoding="utf-8")
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)
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)
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assert xdc_ports
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assert xdc_ports <= top_ports
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def test_apb4_interface_bridge(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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sv2v = shutil.which("sv2v")
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vvp = shutil.which("vvp")
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if iverilog is None or sv2v is None or vvp is None:
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return
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source_list = tmp_path / "apb4_if_bridge.fl"
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source_list.write_text(
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"\n".join(
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[
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/apb4_pure_if.sv"),
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str(ROOT / "rtl/ip/interconnect/apb4_if_bridge.sv"),
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str(ROOT / "tests/rtl/apb4_if_bridge_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "apb4_if_bridge_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "scripts/rtl/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "apb4_if_bridge_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "apb4_if_bridge_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "apb4 interface bridge test passed" in result.stdout
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