mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
d51d58dd25
- Introduced to define formal properties for the sysctrl module. - Updated to include new formal properties and source files. - Renamed to in the bus module and created a new file. - Implemented a testbench for in . - Removed the obsolete test file. - Updated test scripts to reference the new instead of the old RAM module. - Adjusted various test files to ensure compatibility with the new structure and naming conventions.
87 lines
2.6 KiB
Systemverilog
87 lines
2.6 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module pll_rcu_formal;
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localparam [2:0] PLL_IDLE = 3'd0;
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localparam [2:0] PLL_SAFE = 3'd1;
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localparam [2:0] PLL_APPLY = 3'd2;
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localparam [2:0] PLL_WAIT_LOCK = 3'd3;
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localparam [2:0] PLL_SWITCH = 3'd4;
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localparam [2:0] PLL_RESPOND = 3'd5;
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(* anyseq *) (* gclk *)reg clk_i;
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wire rst_n_i;
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wire f_past_valid;
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wire req_valid;
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wire [2:0] req_sel;
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wire req_ready;
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wire rsp_valid;
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wire rsp_ready;
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wire pll_lock;
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wire pll_capable;
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wire [2:0] state;
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wire pll_apply;
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wire select_ext_clk;
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wire active_valid;
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wire safe_clk;
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wire active_lock;
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wire lock_seen_low;
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wire [1:0] error;
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pll_rcu_formal_design u_design (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.f_past_valid (f_past_valid),
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.req_valid (req_valid),
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.req_sel (req_sel),
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.req_ready (req_ready),
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.rsp_valid (rsp_valid),
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.rsp_ready (rsp_ready),
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.pll_lock (pll_lock),
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.pll_capable (pll_capable),
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.state (state),
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.pll_apply (pll_apply),
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.select_ext_clk(select_ext_clk),
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.active_valid (active_valid),
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.safe_clk (safe_clk),
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.active_lock (active_lock),
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.lock_seen_low (lock_seen_low),
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.error (error)
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);
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always @(posedge clk_i) begin
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if (f_past_valid && $past(rst_n_i && req_valid && !req_ready)) begin
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assume (req_valid);
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assume (req_sel == $past(req_sel));
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end
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if (rst_n_i) begin
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assert(!(state == PLL_SAFE || state == PLL_APPLY || state == PLL_WAIT_LOCK) ||
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select_ext_clk);
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assert (!pll_apply || state != PLL_IDLE && state != PLL_SAFE);
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if (f_past_valid && $past(state == PLL_SAFE && !pll_capable)) begin
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assert (state == PLL_RESPOND);
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assert (safe_clk);
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assert (!active_valid);
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assert (error == 2'd1);
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end
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if (f_past_valid && $past(state == PLL_WAIT_LOCK && pll_lock && lock_seen_low)) begin
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assert (state == PLL_SWITCH);
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assert (active_valid);
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assert (!safe_clk);
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assert (active_lock);
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assert (error == 2'd0);
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end
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if (f_past_valid && $past(state == PLL_SWITCH)) begin
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assert (state == PLL_RESPOND);
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assert (!select_ext_clk);
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end
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cover (state == PLL_SWITCH && active_valid && active_lock);
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cover (state == PLL_RESPOND && error == 2'd1);
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cover (state == PLL_RESPOND && error == 2'd2);
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end
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end
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endmodule
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