mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
d51d58dd25
- Introduced to define formal properties for the sysctrl module. - Updated to include new formal properties and source files. - Renamed to in the bus module and created a new file. - Implemented a testbench for in . - Removed the obsolete test file. - Updated test scripts to reference the new instead of the old RAM module. - Adjusted various test files to ensure compatibility with the new structure and naming conventions.
71 lines
2.2 KiB
Systemverilog
71 lines
2.2 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module ribp2apb_formal;
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localparam [1:0] FSM_SETP = 2'd1;
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localparam [1:0] FSM_ENAB = 2'd2;
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(* anyseq *) (* gclk *)reg clk_i;
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wire rst_n_i;
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wire f_past_valid;
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wire rib_valid;
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wire [31:0] rib_addr;
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wire [31:0] rib_wdata;
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wire [ 3:0] rib_wstrb;
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wire rib_ready;
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wire [ 9:0] psel_comb;
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wire [ 9:0] psel_q;
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wire xfer_ready;
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wire [ 1:0] fsm_q;
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ribp2apb_formal_design u_design (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.f_past_valid(f_past_valid),
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.rib_valid (rib_valid),
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.rib_addr (rib_addr),
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.rib_wdata (rib_wdata),
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.rib_wstrb (rib_wstrb),
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.rib_ready (rib_ready),
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.psel_comb (psel_comb),
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.psel_q (psel_q),
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.xfer_ready (xfer_ready),
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.fsm_q (fsm_q)
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);
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always @(posedge clk_i) begin
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if (f_past_valid && $past(rst_n_i && rib_valid && !rib_ready)) begin
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assume (rib_valid);
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assume (rib_addr == $past(rib_addr));
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assume (rib_wdata == $past(rib_wdata));
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assume (rib_wstrb == $past(rib_wstrb));
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end
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if (rst_n_i) begin
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assert ($onehot0(psel_comb));
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assert ($onehot0(psel_q));
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if (rib_ready) begin
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assert (xfer_ready);
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assert (fsm_q == FSM_ENAB);
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end
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if (f_past_valid && $past(rst_n_i && fsm_q == FSM_SETP)) begin
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assert (psel_q == $past(psel_q));
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end
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if (f_past_valid && $past(rst_n_i && fsm_q == FSM_ENAB && !xfer_ready)) begin
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assert (fsm_q == FSM_ENAB);
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assert (psel_q == $past(psel_q));
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end
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cover (fsm_q == FSM_ENAB && rib_ready);
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end
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end
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endmodule
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