mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
d886cd992c
- Updated the file to improve code readability and maintainability by removing commented-out code and adding generated GPIO alternate-function wiring. - Modified to streamline simulation command configurations and removed unnecessary variables. - Introduced a new testbench to validate NMI routing functionality within the SoC topology. - Added comprehensive tests in to ensure the correctness of generated bindings and validate topology constraints. - Adjusted to reflect changes in regression command imports and ensure uniform timeout settings for Verilator simulations.
133 lines
4.9 KiB
Makefile
133 lines
4.9 KiB
Makefile
GENERATED_FL_DIR := $(FLOW_FILELIST_DIR)
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MEMORY_MAP_SOURCE := $(RTL_PATH)/address_map/memory_map.json
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MEMORY_MAP_SCRIPT := $(RTL_PATH)/address_map/generate_memory_map.py
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MEMORY_MAP_DIR := $(VARIANT_ROOT)/generated/memory_map
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MEMORY_MAP_STAMP := $(MEMORY_MAP_DIR)/.stamp
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MEMORY_MAP_RTL_DIR := $(MEMORY_MAP_DIR)/rtl
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MEMORY_MAP_C_DIR := $(MEMORY_MAP_DIR)/include
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MEMORY_MAP_LINKER_DIR := $(MEMORY_MAP_DIR)/linker
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MEMORY_MAP_FILELIST := $(MEMORY_MAP_DIR)/memory_map.fl
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PIN_MAP_SOURCE := $(RTL_PATH)/pin_map/pin_map.json
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PIN_MAP_SCRIPT := $(RTL_PATH)/pin_map/generate_pin_map.py
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PIN_MAP_DIR := $(VARIANT_ROOT)/generated/pin_map
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PIN_MAP_STAMP := $(PIN_MAP_DIR)/.stamp
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PIN_MAP_FILELIST := $(PIN_MAP_DIR)/pin_map.fl
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SOC_TOPOLOGY_SOURCE := $(RTL_PATH)/integration/soc_topology.json
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SOC_TOPOLOGY_SCRIPT := $(RTL_PATH)/integration/generate_soc_topology.py
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SOC_TOPOLOGY_DIR := $(VARIANT_ROOT)/generated/soc_topology
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SOC_TOPOLOGY_STAMP := $(SOC_TOPOLOGY_DIR)/.stamp
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SOC_TOPOLOGY_FILELIST := $(SOC_TOPOLOGY_DIR)/soc_topology.fl
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MPW_STAMP := $(CACHE_ROOT)/stamps/mpw-$(LOCK_DIGEST).prepared
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MPW_OUTPUT_DIR := $(VARIANT_ROOT)/generated/mpw/$(SIM_TOOL_NAME)
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MPW_VARIANT_STAMP := $(MPW_OUTPUT_DIR)/.stamp
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FILELIST_STAMP := $(GENERATED_FL_DIR)/.stamp
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FILELIST_TEMPLATES := $(sort $(wildcard $(ROOT_PATH)/rtl/filelist/pdk_*.fl) \
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$(wildcard $(RTL_PATH)/filelist/*.fl) $(RTL_PATH)/lint.msg)
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$(MPW_STAMP):
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@test -d $(ROOT_PATH)/rtl/managed/mpw/.git || { \
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echo "missing $(ROOT_PATH)/rtl/managed/mpw; run 'make setup-mpw' first" >&2; \
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exit 1; \
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}
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python3 $(ROOT_PATH)/scripts/prepare_mpw.py \
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--lock-file $(CACHE_ROOT)/locks/mpw-prepare.lock
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@mkdir -p $(@D)
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@touch $@
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$(MPW_VARIANT_STAMP): $(MPW_STAMP) $(ROOT_PATH)/scripts/generate_mpw.py
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python3 $(ROOT_PATH)/scripts/generate_mpw.py --root $(ROOT_PATH) \
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--output $(MPW_OUTPUT_DIR) --simu $(SIMU) --core $(CORE) --ip $(IP) \
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--lock-file $(CACHE_ROOT)/locks/mpw.lock
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@mkdir -p $(@D)
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@touch $@
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gen_mpw_code: $(MPW_VARIANT_STAMP)
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$(MEMORY_MAP_STAMP): $(MEMORY_MAP_SOURCE) $(MEMORY_MAP_SCRIPT)
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python3 $(MEMORY_MAP_SCRIPT) --map $(MEMORY_MAP_SOURCE) \
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--output-dir $(MEMORY_MAP_DIR) --have-sram-if $(HAVE_SRAM_IF) --ip $(IP)
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@touch $@
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memory-map: $(MEMORY_MAP_STAMP)
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check-memory-map:
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python3 $(MEMORY_MAP_SCRIPT) --map $(MEMORY_MAP_SOURCE) --check
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$(PIN_MAP_STAMP): $(PIN_MAP_SOURCE) $(PIN_MAP_SCRIPT)
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python3 $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --output-dir $(PIN_MAP_DIR)
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@touch $@
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pin-map: $(PIN_MAP_STAMP)
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check-pin-map:
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python3 $(PIN_MAP_SCRIPT) --map $(PIN_MAP_SOURCE) --check
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$(SOC_TOPOLOGY_STAMP): $(SOC_TOPOLOGY_SOURCE) $(SOC_TOPOLOGY_SCRIPT) $(MEMORY_MAP_SOURCE)
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python3 $(SOC_TOPOLOGY_SCRIPT) --map $(SOC_TOPOLOGY_SOURCE) \
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--memory-map $(MEMORY_MAP_SOURCE) --output-dir $(SOC_TOPOLOGY_DIR)
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@touch $@
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soc-topology: $(SOC_TOPOLOGY_STAMP)
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check-soc-topology:
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python3 $(SOC_TOPOLOGY_SCRIPT) --map $(SOC_TOPOLOGY_SOURCE) \
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--memory-map $(MEMORY_MAP_SOURCE) --check
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$(FILELIST_STAMP): $(FILELIST_TEMPLATES) $(RTL_PATH)/script/generate_filelist.py \
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$(RTL_PATH)/script/filelist.py $(MEMORY_MAP_STAMP) $(PIN_MAP_STAMP) $(SOC_TOPOLOGY_STAMP)
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python3 $(RTL_PATH)/script/generate_filelist.py \
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--output-dir $(GENERATED_FL_DIR) \
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$(foreach define,$(DEF_LIST),--define $(define))
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@touch $@
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generate_filelist: $(FILELIST_STAMP)
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# software
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include $(RTL_PATH)/mk/software.mk
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#====================== filelist ======================
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ifeq ($(PDK), IHP130)
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NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_ihp130.fl
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else ifeq ($(PDK), SKY130)
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NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_sky130.fl
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else ifeq ($(PDK), ICS55)
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NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_ics55.fl
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else ifeq ($(PDK), GF180)
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NET_FLIST := -f $(GENERATED_FL_DIR)/pdk_gf180.fl
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endif
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NET_FLIST += -f $(GENERATED_FL_DIR)/def.fl
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NET_FLIST += -f $(GENERATED_FL_DIR)/sys_def.fl
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NET_FLIST += -f $(GENERATED_FL_DIR)/commonip.fl
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NET_FLIST += -f $(GENERATED_FL_DIR)/inc.fl
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RTL_FLIST := -f $(MEMORY_MAP_FILELIST) -f $(PIN_MAP_FILELIST) -f $(SOC_TOPOLOGY_FILELIST) $(NET_FLIST)
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RTL_FLIST += -f $(GENERATED_FL_DIR)/clusterip.fl
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RTL_FLIST += -f $(GENERATED_FL_DIR)/ip.fl
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RTL_FLIST += -f $(GENERATED_FL_DIR)/tech.fl
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ifeq ($(CORE), PICORV32)
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RTL_FLIST += -f $(GENERATED_FL_DIR)/core_picorv32.fl
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else ifeq ($(CORE), HAZARD3)
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RTL_FLIST += -f $(GENERATED_FL_DIR)/core_hazard3.fl
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else ifeq ($(CORE), MDD)
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RTL_FLIST += -f $(MPW_OUTPUT_DIR)/core/core.fl
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endif
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ifeq ($(IP), MDD)
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RTL_FLIST += -f $(MPW_OUTPUT_DIR)/ip/ip.fl
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endif
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RTL_FLIST += -f $(GENERATED_FL_DIR)/top.fl
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#====================== end ======================
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ifeq ($(SIMU), VCS)
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include $(RTL_PATH)/mk/vcs.mk
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else ifeq ($(SIMU), VERILATOR)
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include $(RTL_PATH)/mk/verilator.mk
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else ifeq ($(SIMU), IVERILOG)
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include $(RTL_PATH)/mk/iverilog.mk
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endif
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.PHONY: gen_mpw_code generate_filelist memory-map check-memory-map pin-map check-pin-map \
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soc-topology check-soc-topology firmware |