mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
952b060a70
Integrate RNG, CRC, WS2812, Crypto, I2S master and the SDIO private AXI owner on SAFE24. Preserve the 128 KiB main SRAM and six private Crypto macros, add product-specific DMA assignments and reject unsupported SDK operations.
Correct APB read strobes, I2S receive assembly and SDIO command timing, backpressure and descriptor retirement. Add pin-level workloads, source-bound evidence checks and publication/commercial consumer compatibility.
Validation of the final P6 worktree: 1726 pytest tests passed with one optional pypdf skip (exit 0, 4021.61 seconds; terminal session 36439). Both PDKs passed both RTL simulators, netlist boot and 38-macro binding checks. Shared formal, Mini compatibility and software/source quality gates passed.
Evidence remains attributed to the retained dirty-worktree snapshots based on b3b30a72cd under build/ics55-tiny-2026-10-12-11-50-2eb98c0e1fae/meta/tiny-r2-p6/. Timing is negative and warning observations are not promoted. This commit does not accept P6, qualify physical operation or enable P7.
281 lines
14 KiB
Python
281 lines
14 KiB
Python
"""Tiny ICS55 SAFE24 platform and the real locked PLL behavioral view."""
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from __future__ import annotations
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import os
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import json
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from pathlib import Path
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import shutil
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import subprocess
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import pytest
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from scripts.check_simulation import DEFAULT_FAILURE
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from scripts.generate_tiny import generate_filelists, platform_values
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from scripts.rtl.generate_memory_map import generate as generate_memory_map
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from scripts.tiny_ics55_platform import inspect_netlist, RAM
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from scripts import tiny_ics55_platform as platform
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ROOT = Path(__file__).resolve().parents[1]
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COMMON = ROOT / "rtl/managed/clusterip/common/rtl"
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PLL = ROOT / ".cache/retrosoc/sources/ics55_ecos_pll/verilog/PLL_TOP.behavioral.v"
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def run(command, **kwargs):
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p = subprocess.run(command, text=True, capture_output=True, **kwargs)
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assert p.returncode == 0, p.stdout + p.stderr
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assert not DEFAULT_FAILURE.search(p.stdout + p.stderr), p.stdout + p.stderr
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return p.stdout
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@pytest.mark.parametrize("simulator", ["iverilog", "verilator"])
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def test_actual_pll_backend(simulator, tmp_path):
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assert shutil.which(simulator) and PLL.is_file(), "required locked input unavailable"
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sources = [COMMON / p for p in ["utils/register.sv", "clkrst/rst_sync.sv", "cdc/cdc_sync.sv",
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"utils/bin2gray.sv", "utils/gray2bin.sv"]]
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sources += [ROOT / "rtl/tech/tc_pll.sv", ROOT / "rtl/tech/tc_pll_ics55_ecos.sv",
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PLL, ROOT / "tests/rtl/tc_pll_ics55_ecos_tb.sv"]
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flags = [f"-I{COMMON}", "-DSV_ASSRT_DISABLE", "-DPDK_ICS55", "-DHAVE_PLL",
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"-DRETROSOC_SOC__TINY"]
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binary = tmp_path / "sim"
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top = "tc_pll_ics55_ecos_tb"
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if simulator == "iverilog":
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command = [simulator, "-g2012", "-s", top, *flags, *map(str, sources), "-o", str(binary)]
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launch = ["vvp", str(binary)]
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else:
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command = [simulator, "--binary", "--timing", "--assert", "-Wno-fatal", "--top-module", top,
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*flags, *map(str, sources), "--Mdir", str(tmp_path / "obj"), "-o", str(binary)]
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launch = [str(binary)]
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run(command, timeout=180, env={**os.environ, "CCACHE_DISABLE": "1"})
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assert "SIM_TEST_PASS ICS55 PLL backend" in run(launch, timeout=60)
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@pytest.mark.parametrize("pdk,pll,technology", [("IHP130", False, 0x02010082), ("ICS55", True, 0x02040037)])
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def test_identity(pdk, pll, technology):
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values = platform_values(pdk, pll)
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assert values["technology"] == technology
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assert values["features0"] == 0x7FFE | pll
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@pytest.mark.parametrize("simulator,synthesis", [("VERILATOR", "NONE"), ("IVERILOG", "NONE"), ("IVERILOG", "YOSYS")])
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def test_flow_specific_inputs(tmp_path, simulator, synthesis):
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generate_filelists(tmp_path, tmp_path / "generated", ["+define+HAVE_PLL"], "ICS55", simulator, synthesis)
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text = (tmp_path / "pdk_selected.fl").read_text()
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assert "IHP-Open-PDK" not in text and "/cache/" not in text.replace("/.cache/", "")
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assert ("PLL_TOP.behavioral.v" in text) == (synthesis == "NONE")
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assert ("ics55_io_sim_cells.sv" in text) == (simulator == "VERILATOR" and synthesis == "NONE")
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def test_default_and_compatibility_configurations():
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output = run(["make", "-s", "SOC=TINY", "config"], cwd=ROOT)
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assert "ics55-tiny.mk" in output and "ICS55" in output
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output = run(["make", "-s", "CONFIG=configs/ci/ihp130-tiny.mk", "config"], cwd=ROOT)
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assert "IHP130" in output
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result = subprocess.run(["make", "-s", "CONFIG=configs/ci/ics55.mk", "SOC=MINI",
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"HAVE_PLL=YES", "TINY_SAFE24_PLL_OFF=YES", "STA=OPENSTA", "config"],
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cwd=ROOT, capture_output=True, text=True)
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assert result.returncode != 0 and "qualified PDK PLL timing profile" in result.stderr
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@pytest.mark.parametrize("changed", [None, "netlist", "json", "config", "script", "missing"])
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def test_consumed_netlist_provenance(tmp_path, monkeypatch, changed):
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monkeypatch.setattr(platform, "check_configuration", lambda *args: None)
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paths = [tmp_path / name for name in ("net.v", "net.v.json", "net.config")]
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for path in paths:
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path.write_text("original")
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report = {"phase": platform.PHASE, "status": "passed",
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"audit_script": platform.b.artifact(Path(platform.__file__)),
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"inputs": [platform.b.artifact(path) for path in paths]}
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if changed in ("netlist", "json", "config"):
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paths[("netlist", "json", "config").index(changed)].write_text("changed")
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elif changed == "script":
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report["audit_script"] = platform.b.artifact(paths[0])
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elif changed == "missing":
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report["inputs"].pop()
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output = tmp_path / "audit.json"
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output.write_text(json.dumps(report))
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if changed:
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with pytest.raises(ValueError):
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platform.verify_netlist(tmp_path, paths[0], paths[2], output)
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else:
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assert platform.verify_netlist(tmp_path, paths[0], paths[2], output) == report
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@pytest.fixture
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def mapped_netlist():
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def cell(kind, **ports):
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return {"type": kind, "connections": {k: [v] for k, v in ports.items()},
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"port_directions": {k: "inout" if k == "PAD" else "output"
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if k in ("Y", "Z", "C", "CKOUT1", "CKOUT2", "CKTST")
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else "input" for k in ports}}
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cells = {"u_clock_buffer": cell("clock_buffer", clk_i=7, clk_o=2),
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"receiver": cell("P65_1233_PBMUX", PAD=1, C=7, IE="1", OE="0", CS="1"),
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"u_soc.u_cpu.u_hazard3_cpu_2port.core.pc_reg": cell("DFF", CK=2),
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"pll": cell("PLL_TOP", EN=3, CKOUT1=4, CKOUT2=5, CKTST=6),
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"low": cell("TIELOH7R", Z=3)}
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cells.update({f"u_soc.u_sram.gen_group[{i // 8}].u_group.gen_bank[{i % 8}].u_ram.u_mem":
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cell(RAM, CLK=2) for i in range(32)})
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cells.update({f"u_soc.u_crypto.u_storage.gen_bank[{i}].gen_macro.u_sram.u_mem":
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cell(RAM, CLK=2) for i in range(6)})
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return {"modules": {
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"retrosoc_tiny_asic": {"ports": {"extclk_i_pad": {"direction": "inout", "bits": [1]},
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"jtag_tck_i_pad": {"direction": "inout", "bits": [11]}},
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"cells": cells},
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"clock_buffer": {"ports": {"clk_i": {"direction": "input", "bits": [100]},
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"clk_o": {"direction": "output", "bits": [101]}},
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"cells": {"u_buf": cell("BUFX0P7H7R", A=100, Y=101)}}}}
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def test_safe24_structural_binding(mapped_netlist):
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result = inspect_netlist(mapped_netlist)
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assert len(result["sram"]) == 32 and result["cpu_clocked_cells"] == 1
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assert len(result["crypto_sram"]) == 6
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assert result["pll_enable"] == 0
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assert result["system_clock_source"]["port"] == "extclk_i_pad"
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assert [c["type"] for c in result["system_clock_source"]["path"]] == [
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"BUFX0P7H7R", "P65_1233_PBMUX"]
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@pytest.mark.parametrize("source", ["0", "1", "x", "z", 99, 11, 4, 2])
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def test_clock_buffer_cannot_hide_invalid_source(mapped_netlist, source):
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# Constants, undriven nets, JTAG, PLL output and feedback all leave the
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# output-side CPU/SRAM net unchanged. The old audit accepted these cases.
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mapped_netlist["modules"]["retrosoc_tiny_asic"]["cells"]["u_clock_buffer"]["connections"]["clk_i"] = [source]
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with pytest.raises(ValueError):
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inspect_netlist(mapped_netlist)
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@pytest.mark.parametrize("mutation", ["missing_ref", "wrong_pad", "disabled_input",
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"unknown_enable", "driven_pad", "unknown_mode",
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"duplicate_sys_driver", "driven_ref", "inverter", "mux"])
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def test_ref24_path_must_be_unambiguous_and_enabled(mapped_netlist, mutation):
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modules = mapped_netlist["modules"]
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top = modules["retrosoc_tiny_asic"]
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cells = top["cells"]
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pad = cells["receiver"]["connections"]
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if mutation == "missing_ref":
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del top["ports"]["extclk_i_pad"]
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elif mutation == "wrong_pad":
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pad["PAD"] = [11]
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elif mutation == "disabled_input":
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pad["IE"] = ["0"]
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elif mutation == "unknown_enable":
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pad["IE"] = ["x"]
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elif mutation == "driven_pad":
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pad["OE"] = ["1"]
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elif mutation == "unknown_mode":
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pad["CS"] = ["x"]
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elif mutation == "duplicate_sys_driver":
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cells["second_driver"] = {"type": "BUFX0P7H7R", "connections": {"A": [7], "Y": [2]},
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"port_directions": {"A": "input", "Y": "output"}}
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elif mutation == "driven_ref":
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cells["pll"]["connections"]["CKOUT1"] = [1]
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else:
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modules["clock_buffer"]["cells"]["u_buf"]["type"] = (
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"INVX0P5H7R" if mutation == "inverter" else "MUX2X1H7R")
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with pytest.raises(ValueError):
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inspect_netlist(mapped_netlist)
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def test_ref24_path_accepts_hierarchical_receiver_and_tie_cells(mapped_netlist):
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modules = mapped_netlist["modules"]
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cells = modules["retrosoc_tiny_asic"]["cells"]
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receiver = cells.pop("receiver")
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receiver["connections"].update(PAD=[100], C=[101], IE=[102], CS=[102], OE=[103])
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cells["receiver"] = {"type": "input_receiver", "connections": {
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"pad": [1], "data": [7], "high": [8], "low": [3]}}
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cells["high"] = {"type": "TIEHIH7R", "connections": {"Z": [8]},
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"port_directions": {"Z": "output"}}
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modules["input_receiver"] = {"ports": {
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"pad": {"direction": "inout", "bits": [100]},
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"data": {"direction": "output", "bits": [101]},
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"high": {"direction": "input", "bits": [102]},
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"low": {"direction": "input", "bits": [103]}}, "cells": {"u_pad": receiver}}
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assert inspect_netlist(mapped_netlist)["system_clock_source"]["port"] == "extclk_i_pad"
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def test_hierarchical_constant_output_is_resolved(mapped_netlist):
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modules = mapped_netlist["modules"]
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modules["constant_zero"] = {"ports": {"result": {"direction": "output", "bits": ["0"]}}, "cells": {}}
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modules["retrosoc_tiny_asic"]["cells"]["low"] = {
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"type": "constant_zero", "connections": {"result": [3]}}
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assert inspect_netlist(mapped_netlist)["pll_enable"] == 0
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@pytest.mark.parametrize("mutation", ["missing_pll", "missing_ram", "live_pll", "unknown_enable",
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"divided_ram", "wrong_cpu", "pll_sys",
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"missing_crypto", "misplaced_crypto", "divided_crypto"])
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def test_unsafe_or_incomplete_mapping_is_rejected(mapped_netlist, mutation):
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cells = mapped_netlist["modules"]["retrosoc_tiny_asic"]["cells"]
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first_ram = "u_soc.u_sram.gen_group[0].u_group.gen_bank[0].u_ram.u_mem"
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first_crypto = "u_soc.u_crypto.u_storage.gen_bank[0].gen_macro.u_sram.u_mem"
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if mutation == "missing_pll":
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del cells["pll"]
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elif mutation == "missing_ram":
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del cells[first_ram]
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elif mutation == "live_pll":
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cells["low"]["type"] = "TIEHIH7R"
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elif mutation == "unknown_enable":
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cells["pll"]["connections"]["EN"] = [99]
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elif mutation == "divided_ram":
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cells[first_ram]["connections"]["CLK"] = [99]
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elif mutation == "wrong_cpu":
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cells["u_soc.u_cpu.u_hazard3_cpu_2port.core.pc_reg"]["connections"]["CK"] = [99]
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elif mutation == "missing_crypto":
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del cells[first_crypto]
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elif mutation == "misplaced_crypto":
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cells["unexpected_private_memory"] = cells.pop(first_crypto)
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elif mutation == "divided_crypto":
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cells[first_crypto]["connections"]["CLK"] = [99]
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else:
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cells["pll"]["connections"]["CKOUT1"] = [2]
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with pytest.raises(ValueError):
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inspect_netlist(mapped_netlist)
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def test_stale_p4_macro_hierarchy_is_rejected(mapped_netlist):
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cells = mapped_netlist["modules"]["retrosoc_tiny_asic"]["cells"]
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first_ram = "u_soc.u_sram.gen_group[0].u_group.gen_bank[0].u_ram.u_mem"
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cells["u_soc.u_sram.gen_memory.gen_bank[0].u_ram.u_mem"] = cells.pop(first_ram)
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with pytest.raises(ValueError, match="hierarchy"):
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inspect_netlist(mapped_netlist)
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def test_tiny_uses_32_actual_ics55_small_macros(tmp_path):
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assert shutil.which("verilator"), "required simulator unavailable"
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generated = tmp_path / "map"
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generate_memory_map(ROOT / "rtl/tiny/address_map/memory_map.json", generated, "YES", 128)
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sram = ROOT / ".cache/retrosoc/pdk/ics55/sram"
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sources = [COMMON / p for p in ["interface/axi4_if.sv", "interface/apb4_if.sv",
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"interface/axi4_addr_gen.sv", "utils/register.sv", "tech/ram.sv"]]
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sources += [ROOT / p for p in ["rtl/tech/tc_sram.sv", "rtl/ip/memory/onchip_ram_reg.sv",
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"rtl/ip/memory/onchip_ram.sv", "tests/rtl/onchip_ram_tb.sv"]]
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sources += [sram / "ics55_ecos_sram_1024x32_m8/verilog/ics55_ecos_sram_1024x32_m8_core.v",
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sram / "ics55_ecos_sram_4096x32_m8/verilog/ics55_ecos_sram_4096x32_m8_stub.v"]
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binary = tmp_path / "sim"
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run(["verilator", "--binary", "--timing", "--assert", "-Wno-fatal", "--top-module", "onchip_ram_tb",
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"-GCapacityKiB=128", "-GIcs55SmallBanks=1", "-DPDK_ICS55", "-DHAVE_SRAM_MACRO", "-DSV_ASSRT_DISABLE",
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*(f"-I{p}" for p in [generated / "rtl", ROOT / "rtl/ip/memory", COMMON, COMMON / "interface"]),
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*map(str, sources), "--Mdir", str(tmp_path / "obj"), "-o", str(binary)],
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timeout=180, env={**os.environ, "CCACHE_DISABLE": "1"})
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assert "on-chip SRAM AXI4 test passed capacity_kib=128" in run([str(binary)], timeout=60)
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@pytest.mark.parametrize("simulator", ["iverilog", "verilator"])
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def test_gpio_readback_preserves_legacy_default(tmp_path, simulator):
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assert shutil.which(simulator), "required simulator unavailable"
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model = ROOT / ("rtl/tech/ics55_io_sim_cells.sv" if simulator == "verilator" else
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"physical/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/verilog/icsIOA_N55_3P3.v")
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sources = [str(ROOT / "rtl/tech/tc_io.sv"), str(model), str(ROOT / "tests/rtl/tc_ics55_gpio_readback_tb.sv")]
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binary = tmp_path / "sim"
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if simulator == "iverilog":
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compile_command = [simulator, "-g2012", "-DPDK_ICS55", "-Dfunctional", "-s",
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"tc_ics55_gpio_readback_tb", *sources, "-o", str(binary)]
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launch = ["vvp", str(binary)]
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else:
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compile_command = [simulator, "--binary", "--timing", "-Wno-fatal", "-DPDK_ICS55",
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"--top-module", "tc_ics55_gpio_readback_tb", *sources,
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"--Mdir", str(tmp_path / "obj"), "-o", str(binary)]
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launch = [str(binary)]
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run(compile_command, timeout=120, env={**os.environ, "CCACHE_DISABLE": "1"})
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assert "SIM_TEST_PASS ICS55 GPIO" in run(launch, timeout=30)
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