mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
152 lines
4.6 KiB
Systemverilog
152 lines
4.6 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "i2s_define.svh"
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interface i2s_if ();
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logic mclk_o;
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logic sclk_o;
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logic lrck_o;
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logic dacdat_o;
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logic adcdat_i;
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logic irq_o;
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modport dut(
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output mclk_o,
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output sclk_o,
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output lrck_o,
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output dacdat_o,
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input adcdat_i,
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output irq_o
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);
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endinterface
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module ribp_i2s (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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output logic dma_tx_stall_o,
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output logic dma_rx_stall_o,
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ribp_if.slave ribp,
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axi4_stream_if.sink tx_axis,
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axi4_stream_if.source rx_axis,
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i2s_if.dut i2s
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// verilog_format: on
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);
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logic s_i2s_mode;
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logic [1:0] s_i2s_format;
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logic s_i2s_recven;
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logic s_i2s_stream_tx_enable;
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logic s_i2s_stream_rx_enable;
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// tx fifo
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logic s_tx_push_valid, s_tx_pio_push_valid, s_tx_full, s_tx_empty;
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logic s_tx_pop_valid, s_tx_pop_ready;
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logic [31:0] s_tx_push_data, s_tx_pio_push_data, s_tx_pop_data;
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logic [7:0] s_tx_elem_num;
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// rx fifo
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logic s_rx_push_valid, s_rx_full, s_rx_empty;
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logic s_rx_pop_valid, s_rx_pio_pop_valid, s_rx_pop_ready;
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logic [31:0] s_rx_push_data, s_rx_pop_data;
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logic [7:0] s_rx_elem_num;
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i2s_reg u_i2s_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp (ribp),
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.mode_o (s_i2s_mode),
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.format_o (s_i2s_format),
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.recven_o (s_i2s_recven),
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.stream_tx_enable_o(s_i2s_stream_tx_enable),
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.stream_rx_enable_o(s_i2s_stream_rx_enable),
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.tx_push_valid_o (s_tx_pio_push_valid),
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.tx_push_data_o (s_tx_pio_push_data),
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.tx_full_i (s_tx_full),
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.tx_elem_num_i (s_tx_elem_num),
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.rx_pop_valid_o (s_rx_pio_pop_valid),
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.rx_pop_data_i (s_rx_pop_data),
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.rx_empty_i (s_rx_empty),
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.rx_elem_num_i (s_rx_elem_num),
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.dma_tx_stall_o (dma_tx_stall_o),
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.dma_rx_stall_o (dma_rx_stall_o)
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);
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assign tx_axis.tready = s_i2s_stream_tx_enable && !s_tx_full;
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assign s_tx_push_valid = s_i2s_stream_tx_enable ?
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(tx_axis.tvalid && tx_axis.tready) : s_tx_pio_push_valid;
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assign s_tx_push_data = s_i2s_stream_tx_enable ? tx_axis.tdata : s_tx_pio_push_data;
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assign rx_axis.tdata = s_rx_pop_data;
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assign rx_axis.tkeep = '1;
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assign rx_axis.tstrb = '1;
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assign rx_axis.tlast = 1'b0;
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assign rx_axis.tid = '0;
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assign rx_axis.tdest = '0;
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assign rx_axis.tuser = '0;
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assign rx_axis.tvalid = s_i2s_stream_rx_enable && !s_rx_empty;
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assign s_rx_pop_valid = s_i2s_stream_rx_enable ?
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(rx_axis.tvalid && rx_axis.tready) : s_rx_pio_pop_valid;
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async_fifo #(
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.DATA_WIDTH (32),
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.DEPTH_POWER(7)
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) u_tx_async_fifo (
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.wr_clk_i (clk_i),
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.wr_rst_n_i(rst_n_i),
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.wr_en_i (s_tx_push_valid),
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.wr_data_i (s_tx_push_data),
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.wr_full_o (s_tx_full),
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.rd_clk_i (clk_aud_i),
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.rd_rst_n_i(rst_aud_n_i),
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.rd_en_i (s_tx_pop_valid),
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.rd_data_o (s_tx_pop_data),
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.rd_empty_o(s_tx_empty),
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.elem_num_o(s_tx_elem_num)
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);
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async_fifo #(
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.DATA_WIDTH (32),
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.DEPTH_POWER(7)
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) u_rx_async_fifo (
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.wr_clk_i (clk_aud_i),
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.wr_rst_n_i(rst_aud_n_i),
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.wr_en_i (s_rx_push_valid & s_i2s_recven),
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.wr_data_i (s_rx_push_data),
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.wr_full_o (s_rx_full),
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.rd_clk_i (clk_i),
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.rd_rst_n_i(rst_n_i),
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.rd_en_i (s_rx_pop_valid),
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.rd_data_o (s_rx_pop_data),
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.rd_empty_o(s_rx_empty),
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.elem_num_o(s_rx_elem_num)
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);
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i2s_core u_i2s_core (
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.clk_i (clk_aud_i),
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.rst_n_i (rst_aud_n_i),
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.mode_i (s_i2s_mode),
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.format_i (s_i2s_format),
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.tx_valid_o(s_tx_pop_valid),
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.tx_data_i (s_tx_pop_data),
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.tx_empty_i(s_tx_empty),
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.rx_valid_o(s_rx_push_valid),
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.rx_data_o (s_rx_push_data),
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.rx_full_i (s_rx_full),
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.i2s (i2s)
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);
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endmodule
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