mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
72 lines
2.8 KiB
Systemverilog
72 lines
2.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// See LICENSE for the complete license text.
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`ifndef SV_ASSRT_DISABLE
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`ifndef SYNTHESIS
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// The design uses rst_n_i asynchronously in state registers while SVA samples
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// it synchronously in disable iff. This is intentional assertion semantics.
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/* verilator lint_off SYNCASYNCNET */
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module axi4_interconnect_sva #(
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parameter int NUM_MASTERS = 3,
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parameter int NUM_TARGETS = 9,
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parameter int MASTER_WIDTH = $clog2(NUM_MASTERS),
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parameter int TARGET_WIDTH = $clog2(NUM_TARGETS)
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic [NUM_MASTERS-1:0][ 1:0] master_state_i,
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input logic [NUM_MASTERS-1:0][TARGET_WIDTH-1:0] master_target_i,
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input logic [NUM_TARGETS-1:0] target_valid_i,
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input logic [NUM_TARGETS-1:0] target_addr_sent_i,
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input logic [NUM_TARGETS-1:0][MASTER_WIDTH-1:0] target_owner_i,
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input logic user_bus_enable_i,
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input logic user_awready_i,
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input logic user_arready_i
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);
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localparam logic [1:0] MASTER_IDLE = 2'd0;
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localparam logic [1:0] MASTER_ACTIVE = 2'd2;
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for (genvar target = 0; target < NUM_TARGETS; target++) begin : GEN_TARGET_OWNERSHIP
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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target_addr_sent_i[target] |-> target_valid_i[target]);
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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target_valid_i[target] |->
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master_state_i[target_owner_i[target]] == MASTER_ACTIVE &&
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master_target_i[target_owner_i[target]] == TARGET_WIDTH'(target));
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for (genvar other = target + 1; other < NUM_TARGETS; other++) begin : GEN_UNIQUE_OWNER
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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target_valid_i[target] && target_valid_i[other] |->
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target_owner_i[target] != target_owner_i[other]);
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end
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end
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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!user_bus_enable_i && master_state_i[1] == MASTER_IDLE |->
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!user_awready_i && !user_arready_i);
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endmodule
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bind axi4_interconnect axi4_interconnect_sva #(
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.NUM_MASTERS(NUM_MASTERS),
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.NUM_TARGETS(NUM_TARGETS)
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) u_axi4_interconnect_sva (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.master_state_i (r_master_state),
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.master_target_i (r_master_target),
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.target_valid_i (r_target_valid),
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.target_addr_sent_i(r_target_addr_sent),
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.target_owner_i (r_target_owner),
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.user_bus_enable_i (user_bus_enable_i),
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.user_awready_i (m_awready[1]),
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.user_arready_i (m_arready[1])
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);
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/* verilator lint_on SYNCASYNCNET */
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`endif
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`endif
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