mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
181 lines
6.4 KiB
Systemverilog
181 lines
6.4 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`ifndef SV_ASSRT_DISABLE
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`ifndef SYNTHESIS
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module rib_bus_sva (
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input logic clk_i,
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input logic rst_n_i,
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input logic fault_cmd_accept_i,
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input logic fault_valid_i,
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input logic access_denied_i,
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input logic cmd_accepted_i,
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input logic arb_locked_i,
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input logic [1:0] arb_owner_i,
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input logic mgmt_valid_i,
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input logic user_valid_i,
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input logic dma_valid_i
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);
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// Fault commands remain active until their local terminal response.
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assert property (@(posedge clk_i) disable iff (!rst_n_i) fault_cmd_accept_i |=> cmd_accepted_i);
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assert property (@(posedge clk_i) disable iff (!rst_n_i) fault_valid_i |-> cmd_accepted_i);
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// A sole management request must acquire ownership rather than being dropped.
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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!arb_locked_i && mgmt_valid_i && !user_valid_i && !dma_valid_i |=>
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arb_locked_i && arb_owner_i == 2'd0);
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// A denied user command can only be accepted by the local error responder.
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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access_denied_i && !cmd_accepted_i |-> fault_cmd_accept_i);
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endmodule
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bind rib_bus rib_bus_sva u_rib_bus_sva (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_cmd_accept_i(s_fault_cmd_hdshk),
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.fault_valid_i (fault_valid_o),
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.arb_locked_i (s_mstr_lock_q),
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.access_denied_i (s_access_denied),
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.cmd_accepted_i (s_cmd_accepted_q),
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.arb_owner_i (s_mstr_id_q),
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.mgmt_valid_i (mgmt_ribp.valid),
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.user_valid_i (user_rib.cmd_valid),
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.dma_valid_i (dma_rib.cmd_valid)
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);
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module rib2apb_sva #(
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parameter int NSLV = 1
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic [NSLV-1:0] psel_comb_i,
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input logic [NSLV-1:0] psel_q_i,
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input logic [ 2:0] fsm_q_i,
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input logic rsp_valid_i,
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input logic [ 1:0] rsp_beat_i,
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input logic rsp_last_i,
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input logic xfer_ready_i
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);
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// Address regions are disjoint and only the registered select drives a response.
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assert property (@(posedge clk_i) disable iff (!rst_n_i) $onehot0(psel_comb_i));
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assert property (@(posedge clk_i) disable iff (!rst_n_i) $onehot0(psel_q_i));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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fsm_q_i == 3'd3 && !xfer_ready_i |=> fsm_q_i == 3'd3);
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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rsp_valid_i |-> rsp_beat_i == 2'd0 && rsp_last_i);
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endmodule
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bind rib2apb rib2apb_sva #(
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.NSLV(NSLV)
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) u_rib2apb_sva (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.psel_comb_i (s_psel_comb),
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.psel_q_i (s_psel_q),
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.fsm_q_i (s_fsm_q),
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.rsp_valid_i (rib.rsp_valid),
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.rsp_beat_i (rib.rsp_beat),
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.rsp_last_i (rib.rsp_last),
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.xfer_ready_i(s_xfer_ready)
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);
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module soc_pll_rcu_sva (
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input logic clk_i,
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input logic rst_n_i,
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input logic [2:0] state_i,
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input logic pll_capable_i,
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input logic pll_apply_i,
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input logic select_ext_clk_i
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);
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localparam logic [2:0] PLL_SAFE = 3'd1;
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localparam logic [2:0] PLL_APPLY = 3'd2;
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localparam logic [2:0] PLL_WAIT_LOCK = 3'd3;
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localparam logic [2:0] PLL_RESPOND = 3'd5;
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// The output remains on the external clock until the PLL switch stage completes.
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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state_i == PLL_SAFE |-> select_ext_clk_i);
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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pll_apply_i |-> state_i inside {PLL_APPLY, PLL_WAIT_LOCK});
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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state_i == PLL_SAFE && !pll_capable_i |=> state_i == PLL_RESPOND);
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endmodule
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bind pll_rcu_controller soc_pll_rcu_sva u_soc_pll_rcu_sva (
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.clk_i (ext_clk_i),
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.rst_n_i (ext_rst_n_i),
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.state_i (s_state_q),
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.pll_capable_i (pll_capable_i),
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.pll_apply_i (pll_apply_o),
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.select_ext_clk_i(select_ext_clk_o)
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);
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module soc_gpio_user_handoff_sva #(
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parameter int DATA_WIDTH = 1
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) (
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input logic clk_i,
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input logic rst_n_i,
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input logic [DATA_WIDTH-1:0] user_sel_i,
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input logic [DATA_WIDTH-1:0] user_handoff_i,
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input logic [DATA_WIDTH-1:0] user_oe_i,
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input logic [DATA_WIDTH-1:0] user_do_i,
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input logic [DATA_WIDTH-1:0] native_oe_i,
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input logic [DATA_WIDTH-1:0] native_do_i,
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input logic [DATA_WIDTH-1:0] open_drain_i,
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input logic [DATA_WIDTH-1:0] selected_oe_i,
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input logic [DATA_WIDTH-1:0] selected_do_i,
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input logic [DATA_WIDTH-1:0] gpio_oe_i,
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input logic [DATA_WIDTH-1:0] gpio_do_i
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);
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// A changing owner first drives output-enable low for a full handoff cycle.
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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selected_oe_i == ((user_sel_i & user_oe_i) | (~user_sel_i & native_oe_i)));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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selected_do_i == ((user_sel_i & user_do_i) | (~user_sel_i & native_do_i)));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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gpio_do_i == (selected_do_i & ~open_drain_i));
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assert property (@(posedge clk_i) disable iff (!rst_n_i)
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gpio_oe_i == (~user_handoff_i & selected_oe_i &
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~(open_drain_i & selected_do_i)));
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endmodule
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bind gpio_core soc_gpio_user_handoff_sva #(
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.DATA_WIDTH(PIN_NUM)
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) u_soc_gpio_user_handoff_sva (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.user_sel_i (user_select_i),
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.user_handoff_i(user_handoff_i),
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.user_oe_i (user_gpio.oe_o),
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.user_do_i (user_gpio.do_o),
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.native_oe_i (s_native_oe),
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.native_do_i (s_native_data),
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.open_drain_i (open_drain_i),
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.selected_oe_i (s_selected_oe),
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.selected_do_i (s_selected_data),
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.gpio_oe_i (gpio.oe_o),
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.gpio_do_i (gpio.do_o)
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);
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`include "soc_irq_sva.svh"
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`endif
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`endif
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