mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
23 lines
874 B
Plaintext
23 lines
874 B
Plaintext
/clusterip/common/rtl/interface/apb4_if.sv
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/clusterip/common/rtl/interface/apb4_pure_if.sv
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/clusterip/common/rtl/interface/ahbl_if.sv
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/clusterip/common/rtl/interface/axi4_if.sv
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/clusterip/common/rtl/interface/axi4_stream_if.sv
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/clusterip/common/rtl/interface/ribp_if.sv
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/clusterip/common/rtl/interface/ram_if.sv
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/top/rib_if.sv
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/clusterip/common/rtl/utils/register.sv
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/top/soc_common_fifo.sv
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/clusterip/common/rtl/utils/spill_register.sv
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/clusterip/common/rtl/stream/round_robin_arbiter.sv
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/clusterip/common/rtl/utils/lfsr.sv
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/clusterip/common/rtl/utils/gray2bin.sv
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/clusterip/common/rtl/utils/edge_det.sv
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/clusterip/common/rtl/cdc/cdc_sync.sv
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/clusterip/common/rtl/cdc/cdc_rst_ctrlr.sv
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/clusterip/common/rtl/cdc/cdc_2phase.sv
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/top/soc_common_cdc.sv
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/clusterip/common/rtl/clkrst/clk_int_div.sv
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/clusterip/common/rtl/clkrst/rst_sync.sv
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/clusterip/common/rtl/clkrst/counter.sv
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