mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
106 lines
2.8 KiB
Systemverilog
106 lines
2.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// See LICENSE for the complete license text.
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`include "axi4_define.svh"
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module axi4_error_slave #(
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parameter logic [1:0] RESPONSE = `AXI4_RESP_DECODE_ERROR
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) (
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input logic clk_i,
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input logic rst_n_i,
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axi4_if.slave axi4
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);
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localparam logic [1:0] FSM_IDLE = 2'd0;
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localparam logic [1:0] FSM_WRITE = 2'd1;
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localparam logic [1:0] FSM_WRITE_RESP = 2'd2;
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localparam logic [1:0] FSM_READ_RESP = 2'd3;
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logic [1:0] s_fsm_d, s_fsm_q;
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logic s_id_d, s_id_q;
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logic [7:0] s_len_d, s_len_q;
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logic [7:0] s_beat_d, s_beat_q;
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assign axi4.awready = (s_fsm_q == FSM_IDLE) && !axi4.arvalid;
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assign axi4.arready = (s_fsm_q == FSM_IDLE);
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assign axi4.wready = (s_fsm_q == FSM_WRITE);
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assign axi4.bid = s_id_q;
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assign axi4.bresp = RESPONSE;
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assign axi4.buser = '0;
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assign axi4.bvalid = (s_fsm_q == FSM_WRITE_RESP);
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assign axi4.rid = s_id_q;
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assign axi4.rdata = '0;
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assign axi4.rresp = RESPONSE;
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assign axi4.rlast = (s_beat_q == s_len_q);
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assign axi4.ruser = '0;
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assign axi4.rvalid = (s_fsm_q == FSM_READ_RESP);
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always_comb begin
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s_fsm_d = s_fsm_q;
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s_id_d = s_id_q;
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s_len_d = s_len_q;
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s_beat_d = s_beat_q;
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unique case (s_fsm_q)
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FSM_IDLE: begin
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s_beat_d = '0;
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if (axi4.arvalid && axi4.arready) begin
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s_id_d = axi4.arid;
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s_len_d = axi4.arlen;
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s_fsm_d = FSM_READ_RESP;
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end else if (axi4.awvalid && axi4.awready) begin
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s_id_d = axi4.awid;
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s_len_d = axi4.awlen;
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s_fsm_d = FSM_WRITE;
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end
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end
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FSM_WRITE: begin
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if (axi4.wvalid && axi4.wready) begin
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if ((s_beat_q == s_len_q) || axi4.wlast) begin
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s_fsm_d = FSM_WRITE_RESP;
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end else begin
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s_beat_d = s_beat_q + 1'b1;
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end
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end
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end
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FSM_WRITE_RESP: begin
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if (axi4.bvalid && axi4.bready) s_fsm_d = FSM_IDLE;
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end
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FSM_READ_RESP: begin
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if (axi4.rvalid && axi4.rready) begin
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if (s_beat_q == s_len_q) begin
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s_fsm_d = FSM_IDLE;
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end else begin
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s_beat_d = s_beat_q + 1'b1;
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end
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end
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end
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default: s_fsm_d = FSM_IDLE;
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endcase
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end
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dffr #(2) u_fsm_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_fsm_d),
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.dat_o (s_fsm_q)
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);
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dffr #(1) u_id_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_id_d),
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.dat_o (s_id_q)
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);
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dffr #(8) u_len_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_len_d),
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.dat_o (s_len_q)
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);
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dffr #(8) u_beat_dffr (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_beat_d),
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.dat_o (s_beat_q)
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);
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endmodule
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