mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
367 lines
11 KiB
Systemverilog
367 lines
11 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`include "mmap_define.svh"
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`include "soc_irq_config.svh"
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module apb4_periph (
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// verilog_format: off -- preserve reviewed column alignment
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input logic clk_i,
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input logic rst_n_i,
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input logic clk_aud_i,
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input logic rst_aud_n_i,
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input logic clk_ulpi_i,
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input logic debug_halted_i,
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input logic timebase_tick_i,
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axi4_if.slave cfg_axi4,
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axi4_if.slave psram_axi4,
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axi4_if.slave xpi_axi4,
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axi4_if.master spisd_axi4,
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axi4_if.slave opipsram_axi4,
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gpio_if.dut gpio,
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user_gpio_if.padctrl user_gpio,
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uart_if.dut uart,
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psram_if.dut psram,
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spi_if.dut spisd,
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i2c_if.dut i2c0,
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i2s_if.dut i2s,
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ws2812_if.dut ws2812,
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xpi_if.dut xpi,
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axi4_if.master dma_axi4,
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axi4_if.master sdio0_axi4,
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axi4_if.master sdio1_axi4,
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axi4_if.master usb2_axi4,
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sysctrl_if.dut sysctrl,
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pll_ctrl_if.sysctrl pll_ctrl,
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apb4_if.master sdram_cfg,
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dvp_if.dut dvp,
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sdio_if.dut sdio0,
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sdio_if.dut sdio1,
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usb2_ulpi_if.dut usb2,
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opipsram_if.dut opipsram,
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i2c_if.dut i2c1,
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input logic fault_valid_i,
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input logic [31:0] fault_addr_i,
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input logic [3:0] fault_wstrb_i,
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input logic fault_reserved_i,
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output logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] irq_o
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// verilog_format: on
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);
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// Generated timed and pure scalar APB interfaces preserve FPGA compatibility.
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`include "apb4_periph_interfaces.svh"
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`include "apb4_periph_bridges.svh"
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_i2s_tx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_i2s_rx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_dvp_rx_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_crypto_in_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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axi4_stream_if #(
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.DEST_WIDTH(1),
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.USER_WIDTH(1)
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) u_crypto_out_axis_if (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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clint_if u_clint_if ();
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dma_req_if u_dma_req_if ();
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logic s_dma_i2s_tx_stall, s_dma_i2s_rx_stall;
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logic s_dma_xpi_tx_stall, s_dma_xpi_rx_stall;
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logic s_dma_uart_tx_stall, s_dma_uart_rx_stall;
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logic s_dma_i2c0_tx_stall, s_dma_i2c0_rx_stall;
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logic s_dma_i2c1_tx_stall, s_dma_i2c1_rx_stall;
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logic s_dma_xfer_done;
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logic s_dma_irq;
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logic s_dma_crypto_in_proc;
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logic s_dma_crypto_out_proc;
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logic s_crypto_irq;
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logic s_usb2_irq;
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logic s_tim0_irq, s_tim1_irq;
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logic s_dvp_irq;
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logic s_xpi_irq;
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`ifdef PDK_GF180
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b1;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b1;
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`elsif PDK_ICS55
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b1;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b1;
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`elsif PDK_SKY130
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b1;
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localparam bit GPIO_HAS_PULL_UP = 1'b0;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b0;
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`else
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localparam bit GPIO_HAS_INPUT_CMOS = 1'b0;
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localparam bit GPIO_HAS_PULL_UP = 1'b0;
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localparam bit GPIO_HAS_PULL_DOWN = 1'b0;
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`endif
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axi42apb4_periph u_axi42apb4_periph (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (cfg_axi4),
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`include "apb4_periph_connections.svh"
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);
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assign u_dma_req_if.i2s_tx_proc = ~s_dma_i2s_tx_stall;
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assign u_dma_req_if.i2s_rx_proc = ~s_dma_i2s_rx_stall;
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assign u_dma_req_if.qspi_tx_proc = ~s_dma_xpi_tx_stall;
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assign u_dma_req_if.qspi_rx_proc = ~s_dma_xpi_rx_stall;
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assign u_dma_req_if.uart_tx_proc = ~s_dma_uart_tx_stall;
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assign u_dma_req_if.uart_rx_proc = ~s_dma_uart_rx_stall;
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assign u_dma_req_if.i2c0_tx_proc = ~s_dma_i2c0_tx_stall;
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assign u_dma_req_if.i2c0_rx_proc = ~s_dma_i2c0_rx_stall;
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assign u_dma_req_if.i2c1_tx_proc = ~s_dma_i2c1_tx_stall;
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assign u_dma_req_if.i2c1_rx_proc = ~s_dma_i2c1_rx_stall;
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assign u_dma_req_if.crypto_in_proc = s_dma_crypto_in_proc;
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assign u_dma_req_if.crypto_out_proc = s_dma_crypto_out_proc;
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`include "apb4_periph_irq_bindings.svh"
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// verilog_format: off -- preserve reviewed column alignment
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apb4_gpio #(
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.UserBaseAddr (`SOC_ADDR_APB4_GPIO_BASE),
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.AdminBaseAddr(`SOC_ADDR_APB4_GPIO_ADMIN_BASE),
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.HasInputCmos (GPIO_HAS_INPUT_CMOS),
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.HasPullUp (GPIO_HAS_PULL_UP),
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.HasPullDown (GPIO_HAS_PULL_DOWN)
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) u_apb4_gpio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_gpio_apb4_if),
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.gpio (gpio),
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.user_gpio (user_gpio)
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);
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// verilog_format: on
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apb4_uart u_apb4_uart (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_uart_tx_stall),
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.dma_rx_stall_o(s_dma_uart_rx_stall),
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.apb4 (u_uart_apb4_if),
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.uart (uart)
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);
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apb4_timer u_apb4_timer0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(debug_halted_i),
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.apb4 (u_tim0_apb4_if),
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.irq_o (s_tim0_irq)
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);
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apb4_timer u_apb4_timer1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.debug_halted_i(debug_halted_i),
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.apb4 (u_tim1_apb4_if),
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.irq_o (s_tim1_irq)
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);
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apb4_psram u_apb4_psram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.cfg_apb4(u_psram_apb4_if),
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.mem_axi4(psram_axi4),
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.psram (psram)
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);
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apb4_spisd u_apb4_spisd (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_spisd_apb4_if),
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.dma_axi4(spisd_axi4),
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.spi (spisd)
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);
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apb4_i2c u_apb4_i2c0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_i2c0_tx_stall),
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.dma_rx_stall_o(s_dma_i2c0_rx_stall),
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.apb4 (u_i2c0_apb4_if),
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.i2c (i2c0)
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);
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apb4_i2s u_apb4_i2s (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_aud_i (clk_aud_i),
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.rst_aud_n_i (rst_aud_n_i),
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.dma_tx_stall_o(s_dma_i2s_tx_stall),
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.dma_rx_stall_o(s_dma_i2s_rx_stall),
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.apb4 (u_i2s_apb4_if),
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.tx_axis (u_i2s_tx_axis_if),
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.rx_axis (u_i2s_rx_axis_if),
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.i2s (i2s)
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);
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apb4_ws2812 u_apb4_ws2812 (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.apb4 (u_ws2812_apb4_if),
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.ws2812 (ws2812)
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);
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apb4_xpi u_apb4_xpi (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_i(s_dma_xfer_done),
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.dma_tx_stall_o (s_dma_xpi_tx_stall),
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.dma_rx_stall_o (s_dma_xpi_rx_stall),
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.irq_o (s_xpi_irq),
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.apb4 (u_xpi_apb4_if),
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.mem_axi4 (xpi_axi4),
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.xpi (xpi)
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);
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apb4_dma #(
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.NumChannels(6)
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) u_apb4_dma (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_xfer_done_o(s_dma_xfer_done),
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.irq_o (s_dma_irq),
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.hw_trg (u_dma_req_if),
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.apb4 (u_dma_apb4_if),
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.axi4 (dma_axi4),
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.i2s_tx_axis (u_i2s_tx_axis_if),
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.i2s_rx_axis (u_i2s_rx_axis_if),
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.dvp_rx_axis (u_dvp_rx_axis_if),
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.crypto_in_axis (u_crypto_in_axis_if),
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.crypto_out_axis(u_crypto_out_axis_if)
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);
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apb4_crypto u_apb4_crypto (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_input_proc_o (s_dma_crypto_in_proc),
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.dma_output_proc_o(s_dma_crypto_out_proc),
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.irq_o (s_crypto_irq),
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.apb4 (u_crypto_apb4_if),
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.crypto_in_axis (u_crypto_in_axis_if),
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.crypto_out_axis (u_crypto_out_axis_if)
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);
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apb4_sysctrl u_apb4_sysctrl (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.apb4 (u_sysctrl_apb4_if),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl)
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);
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apb4_clint u_apb4_clint (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.timebase_tick_i(timebase_tick_i),
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.apb4 (u_clint_apb4_if),
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.clint (u_clint_if)
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);
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axi4s_dvp u_axi4_dvp (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.apb4 (u_dvp_apb4_if),
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.rx_axis(u_dvp_rx_axis_if),
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.dvp (dvp),
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.irq_o (s_dvp_irq)
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);
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apb4_sdio u_apb4_sdio0 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_sdio0_apb4_if),
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.dma_axi4(sdio0_axi4),
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.sdio (sdio0)
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);
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apb4_sdio u_apb4_sdio1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (u_sdio1_apb4_if),
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.dma_axi4(sdio1_axi4),
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.sdio (sdio1)
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);
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apb4_usb2 u_apb4_usb2 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_ulpi_i(clk_ulpi_i),
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.apb4 (u_usb2_apb4_if),
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.dma_axi4 (usb2_axi4),
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.irq_o (s_usb2_irq),
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.ulpi (usb2)
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);
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apb4_opipsram u_apb4_opipsram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.clk_phy_i (clk_i),
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.rst_phy_n_i(rst_n_i),
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.cfg_apb4 (u_opipsram_apb4_if),
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.mem_axi4 (opipsram_axi4),
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.psram (opipsram)
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);
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apb4_i2c u_apb4_i2c1 (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(s_dma_i2c1_tx_stall),
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.dma_rx_stall_o(s_dma_i2c1_rx_stall),
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.apb4 (u_i2c1_apb4_if),
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.i2c (i2c1)
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);
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endmodule
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