mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
97 lines
2.7 KiB
Systemverilog
97 lines
2.7 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module usb2_packet_ram_tb;
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logic s_clk;
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logic s_rst_n;
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logic s_write;
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logic s_read;
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logic [11:0] s_addr;
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logic [31:0] s_write_data;
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logic s_inject_single;
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logic s_inject_double;
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logic [31:0] s_read_data;
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logic s_read_valid;
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logic s_corrected;
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logic s_uncorrectable;
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usb2_packet_ram #(
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.EnableFaultInjection(1'b1)
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) u_packet_ram (
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.clk_i (s_clk),
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.rst_n_i (s_rst_n),
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.write_i (s_write),
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.read_i (s_read),
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.addr_i (s_addr),
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.write_data_i (s_write_data),
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.inject_single_i(s_inject_single),
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.inject_double_i(s_inject_double),
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.read_data_o (s_read_data),
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.read_valid_o (s_read_valid),
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.corrected_o (s_corrected),
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.uncorrectable_o(s_uncorrectable)
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);
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always #5 s_clk = ~s_clk;
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task automatic write_word(input logic [11:0] addr_i, input logic [31:0] data_i,
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input logic single_i, input logic double_i);
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begin
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@(negedge s_clk);
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s_addr = addr_i;
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s_write_data = data_i;
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s_inject_single = single_i;
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s_inject_double = double_i;
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s_write = 1'b1;
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@(negedge s_clk);
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s_write = 1'b0;
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s_inject_single = 1'b0;
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s_inject_double = 1'b0;
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end
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endtask
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task automatic read_word(input logic [11:0] addr_i);
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begin
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@(negedge s_clk);
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s_addr = addr_i;
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s_read = 1'b1;
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@(posedge s_clk);
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#1;
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s_read = 1'b0;
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end
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endtask
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initial begin
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s_clk = 1'b0;
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s_rst_n = 1'b0;
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s_write = 1'b0;
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s_read = 1'b0;
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s_addr = '0;
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s_write_data = '0;
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s_inject_single = 1'b0;
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s_inject_double = 1'b0;
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repeat (2) @(negedge s_clk);
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s_rst_n = 1'b1;
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write_word(12'h010, 32'h1357_9BDF, 1'b0, 1'b0);
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read_word(12'h010);
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if (!s_read_valid || s_corrected || s_uncorrectable || (s_read_data != 32'h1357_9BDF)) begin
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$fatal(1, "USB2 packet RAM clean read failed");
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end
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write_word(12'h011, 32'h2468_ACE0, 1'b1, 1'b0);
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read_word(12'h011);
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if (!s_read_valid || !s_corrected || s_uncorrectable || (s_read_data != 32'h2468_ACE0)) begin
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$fatal(1, "USB2 packet RAM single-bit correction failed");
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end
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write_word(12'h012, 32'h55AA_F00D, 1'b0, 1'b1);
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read_word(12'h012);
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if (!s_read_valid || !s_uncorrectable) begin
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$fatal(1, "USB2 packet RAM double-bit detection failed");
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end
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$display("USB2 packet RAM ECC test passed");
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$finish;
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end
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endmodule
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