mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
181 lines
6.7 KiB
Systemverilog
181 lines
6.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module usb2_scheduler_tb;
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logic s_clk = 1'b0;
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logic s_rst_n = 1'b0;
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logic s_reinitialize = 1'b0;
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logic [13:0] s_frame = 14'd0;
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logic [ 7:0][31:0] s_endpoint_cfg = '0;
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logic [ 7:0][31:0] s_endpoint_ram_in = '0;
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logic [ 7:0][31:0] s_endpoint_ram_out = '0;
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logic [ 7:0][31:0] s_endpoint_desc_in = '0;
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logic [ 7:0][31:0] s_endpoint_desc_out = '0;
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logic [ 7:0][31:0] s_endpoint_command = '0;
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logic [15:0][31:0] s_channel_cfg = '0;
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logic [15:0][31:0] s_channel_target = '0;
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logic [15:0][31:0] s_channel_interval = '0;
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logic [15:0][31:0] s_channel_ram = '0;
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logic [15:0][31:0] s_channel_desc = '0;
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logic [15:0][31:0] s_channel_command = '0;
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logic s_work_valid;
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logic [63:0] s_work_data;
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logic s_result_valid = 1'b0;
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logic [63:0] s_result_data = '0;
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logic s_fill_ready = 1'b0;
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logic s_dma_start;
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logic s_dma_done = 1'b0;
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logic s_buffer_event_valid = 1'b0;
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logic [ 2:0] s_buffer_event_data = 3'd0;
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logic s_busy;
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logic [ 3:0] s_seen_index [0:3];
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integer s_work_count = 0;
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always #5 s_clk = ~s_clk;
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always_ff @(posedge s_clk) begin
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s_dma_done <= 1'b0;
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s_buffer_event_valid <= 1'b0;
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s_result_valid <= 1'b0;
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if (s_dma_start) begin
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s_dma_done <= 1'b1;
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s_buffer_event_valid <= 1'b1;
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end
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if (s_work_valid) begin
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s_seen_index[s_work_count] <= s_work_data[usb2_pkg::USB2_WORK_INDEX_LSB+:4];
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s_work_count <= s_work_count + 1;
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s_result_data <= 64'd0;
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s_result_data[usb2_pkg::USB2_RESULT_ROLE_LSB+:2] <= usb2_pkg::Usb2RoleHost;
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s_result_data[usb2_pkg::USB2_RESULT_INDEX_LSB+:4] <=
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s_work_data[usb2_pkg::USB2_WORK_INDEX_LSB+:4];
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s_result_data[usb2_pkg::USB2_RESULT_LENGTH_LSB+:15] <= 15'd4;
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s_result_valid <= 1'b1;
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end
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end
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usb2_scheduler u_scheduler (
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.clk_i (s_clk),
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.rst_n_i (s_rst_n),
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.enable_i (1'b1),
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.abort_i (1'b0),
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.reinitialize_i (s_reinitialize),
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.perf_clear_i (1'b0),
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.high_speed_i (1'b1),
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.frame_i (s_frame),
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.active_role_i (usb2_pkg::Usb2RoleHost),
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.endpoint_cfg_i (s_endpoint_cfg),
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.endpoint_ram_in_i (s_endpoint_ram_in),
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.endpoint_ram_out_i (s_endpoint_ram_out),
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.endpoint_desc_in_i (s_endpoint_desc_in),
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.endpoint_desc_out_i (s_endpoint_desc_out),
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.endpoint_command_i (s_endpoint_command),
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.endpoint_complete_clear_in_i (32'd0),
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.endpoint_complete_clear_out_i(32'd0),
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.channel_cfg_i (s_channel_cfg),
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.channel_target_i (s_channel_target),
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.channel_interval_i (s_channel_interval),
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.channel_ram_i (s_channel_ram),
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.channel_desc_i (s_channel_desc),
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.channel_command_i (s_channel_command),
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.work_valid_o (s_work_valid),
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.work_ready_i (1'b1),
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.work_data_o (s_work_data),
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.result_valid_i (s_result_valid),
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.result_ready_o (),
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.result_data_i (s_result_data),
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.fill_cmd_valid_o (),
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.fill_cmd_ready_i (s_fill_ready),
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.fill_cmd_data_o (),
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.drain_cmd_valid_o (),
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.drain_cmd_ready_i (1'b1),
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.drain_cmd_data_o (),
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.buffer_event_valid_i (s_buffer_event_valid),
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.buffer_event_ready_o (),
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.buffer_event_data_i (s_buffer_event_data),
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.dma_start_o (s_dma_start),
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.dma_abort_o (),
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.dma_memory_to_packet_o (),
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.dma_desc_base_o (),
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.dma_transfer_bytes_o (),
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.dma_busy_i (1'b0),
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.dma_done_i (s_dma_done),
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.dma_error_i (1'b0),
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.dma_error_code_i (8'd0),
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.dma_current_desc_i (32'd0),
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.dma_bytes_done_i (32'd4),
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.retry_i (1'b0),
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.endpoint_pending_in_o (),
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.endpoint_pending_out_o (),
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.endpoint_complete_in_o (),
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.endpoint_complete_out_o (),
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.endpoint_status_o (),
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.endpoint_bytes_in_o (),
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.endpoint_bytes_out_o (),
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.channel_status_o (),
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.channel_bytes_o (),
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.irq_event_o (),
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.error_capture_o (),
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.error_status_o (),
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.error_code_o (),
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.error_info_o (),
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.error_desc_addr_o (),
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.error_buffer_addr_o (),
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.perf_tx_bytes_o (),
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.perf_rx_bytes_o (),
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.perf_packets_o (),
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.perf_retries_o (),
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.perf_irq_count_o (),
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.busy_o (s_busy)
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);
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task automatic issue_channel(input int channel_i);
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begin
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@(negedge s_clk);
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s_channel_command[channel_i] = 32'd1;
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@(negedge s_clk);
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s_channel_command[channel_i] = 32'd0;
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end
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endtask
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initial begin
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for (int channel = 0; channel < 16; channel++) begin
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s_channel_cfg[channel] = 32'h0040_0009;
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s_channel_ram[channel] = 32'h0004_0000;
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s_channel_desc[channel] = 32'h4000_0000 + (32'(channel) << 5);
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end
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s_channel_cfg[3][3:2] = usb2_pkg::Usb2TransferInterrupt;
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s_channel_interval[3] = 32'd8;
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repeat (4) @(posedge s_clk);
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s_rst_n = 1'b1;
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issue_channel(1);
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wait (s_busy);
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issue_channel(2);
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repeat (2) @(posedge s_clk);
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s_fill_ready = 1'b1;
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wait (s_work_count == 2);
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wait (!s_busy);
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if ((s_seen_index[0] != 4'd1) || (s_seen_index[1] != 4'd2)) begin
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$fatal(1, "USB2 busy command queue dropped or reordered work");
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end
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issue_channel(3);
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wait (s_work_count == 3);
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wait (!s_busy);
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s_frame = 14'd1;
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issue_channel(3);
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repeat (8) @(posedge s_clk);
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if (s_work_count != 3) $fatal(1, "USB2 periodic command ran before its interval");
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s_frame = 14'd8;
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wait (s_work_count == 4);
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if (s_seen_index[3] != 4'd3) $fatal(1, "USB2 periodic command was not retained");
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@(negedge s_clk);
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s_reinitialize = 1'b1;
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@(negedge s_clk);
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s_reinitialize = 1'b0;
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$display("USB2 scheduler queue and interval passed");
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$finish;
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end
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endmodule
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