mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
e4e5546dbc
- Deleted the UART interface and related components from the RTL design, including the UART TX/RX signals and instances. - Removed the timer interface and its associated files from the project, including the timer definitions and references in the integration files. - Updated the APB target configurations to reflect the removal of the UART and timer components, ensuring the IRQ and memory map configurations are consistent. - Adjusted the formal verification properties and testbenches to exclude references to the removed components. - Cleaned up the integration documentation to accurately describe the current state of the system without the UART and timer interfaces.
394 lines
16 KiB
Python
394 lines
16 KiB
Python
"""Tests for the generated Mini SoC internal integration bindings."""
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from __future__ import annotations
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import json
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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TOPOLOGY = ROOT / "rtl/mini/integration/soc_topology.json"
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GENERATOR = ROOT / "rtl/mini/integration/generate_soc_topology.py"
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MEMORY_MAP = ROOT / "rtl/mini/address_map/memory_map.json"
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MEMORY_MAP_GENERATOR = ROOT / "rtl/mini/address_map/generate_memory_map.py"
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def generate(output_dir: Path) -> None:
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subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--map",
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str(TOPOLOGY),
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"--memory-map",
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str(MEMORY_MAP),
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"--output-dir",
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str(output_dir),
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],
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check=True,
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)
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def validate(topology: Path) -> subprocess.CompletedProcess[str]:
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return subprocess.run(
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[
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sys.executable,
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str(GENERATOR),
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"--map",
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str(topology),
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"--memory-map",
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str(MEMORY_MAP),
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"--check",
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],
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text=True,
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capture_output=True,
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)
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def write_invalid_topology(tmp_path: Path, document: dict[str, object]) -> Path:
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path = tmp_path / "invalid_topology.json"
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path.write_text(json.dumps(document), encoding="utf-8")
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return path
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def test_topology_generates_complete_rib_apb_and_gpio_bindings(tmp_path: Path) -> None:
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generate(tmp_path)
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interfaces = (tmp_path / "rtl/ribp_interfaces.svh").read_text(encoding="utf-8")
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routes = (tmp_path / "rtl/ribp_routes.svh").read_text(encoding="utf-8")
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gpio = (tmp_path / "rtl/soc_gpio_alt_bindings.svh").read_text(encoding="utf-8")
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apb_interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
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apb_declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
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apb_routes = (tmp_path / "rtl/soc_apb_request_routes.svh").read_text(encoding="utf-8")
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apb_response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
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fabric = (tmp_path / "rtl/soc_fabric_interfaces.svh").read_text(encoding="utf-8")
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bus_fabric = (tmp_path / "rtl/soc_bus_fabric.svh").read_text(encoding="utf-8")
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irq_config = (tmp_path / "rtl/soc_irq_config.svh").read_text(encoding="utf-8")
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rib_irq = (tmp_path / "rtl/ribp_irq_bindings.svh").read_text(encoding="utf-8")
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apb_irq = (tmp_path / "rtl/soc_apb_irq_bindings.svh").read_text(encoding="utf-8")
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irq_wiring = (tmp_path / "rtl/soc_irq_wiring.svh").read_text(encoding="utf-8")
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irq_sva = (tmp_path / "rtl/soc_irq_sva.svh").read_text(encoding="utf-8")
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filelist = (tmp_path / "soc_topology.fl").read_text(encoding="utf-8")
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assert interfaces.count("ribp_if u_") == 18
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assert "nmi_if" not in interfaces
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assert "soc_nmi" not in interfaces
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assert "assign s_slv_sel_d[17] = u_i2c1_ribp_if.valid;" in routes
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assert "assign s_slv_resp_err[17] = u_i2c1_ribp_if.resp_err;" in routes
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assert "assign ribp.resp_err = |(s_slv_sel_q & s_slv_ready & s_slv_resp_err);" in routes
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assert "assign s_xpi_region_sel[1] = (ribp.addr <= `SOC_ADDR_FLASH_END);" in routes
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assert "assign u_sdio_ribp_if.valid = 1'b0;" in routes
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assert gpio.count("// GPIO") == 64
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assert "u_uart1_if" not in gpio
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assert "assign u_gpio_if.alt0_do_i[0] = 1'b0;" in gpio
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assert "assign u_gpio_if.alt0_oe_i[0] = 1'b0;" in gpio
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assert "assign u_gpio_if.alt0_do_i[1] = 1'b0;" in gpio
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assert "assign u_gpio_if.alt0_oe_i[1] = 1'b0;" in gpio
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assert "assign u_gpio_if.alt1_do_i[0] = u_ps2_if.ps2_clk_o;" in gpio
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assert "assign u_gpio_if.alt1_oe_i[0] = u_ps2_if.ps2_clk_oe_o;" in gpio
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assert "assign u_gpio_if.alt1_do_i[1] = u_ps2_if.ps2_dat_o;" in gpio
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assert "assign u_gpio_if.alt1_oe_i[1] = u_ps2_if.ps2_dat_oe_o;" in gpio
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assert "assign u_gpio_if.alt1_do_i[2] = u_ws2812_if.dat_o;" in gpio
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assert "assign u_pwm_if.sync_i = u_gpio_if.di_i[2];" in gpio
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assert "assign u_gpio_if.alt0_do_i[3] = u_pwm_if.pwm_o[0];" in gpio
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assert "assign u_gpio_if.alt0_oe_i[3] = u_pwm_if.oe_o[0];" in gpio
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assert "assign u_pwm_if.fault_i = u_gpio_if.di_i[9];" in gpio
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assert "assign u_pwm_if.capture_i[0] = u_gpio_if.di_i[30];" in gpio
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assert "assign u_pwm_if.capture_i[1] = u_gpio_if.di_i[31];" in gpio
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assert "assign u_gpio_if.alt1_do_i[22] = u_psram_if.nss_o[0];" in gpio
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assert "s_tmr_capch" not in gpio
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assert apb_interfaces.count("apb4_if u_") == 8
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assert "apb4_pure_if u_archinfo_apb_pure_if ();" in apb_interfaces
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assert "assign user_ip.paddr = s_addr_q;" in apb_routes
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assert "({32{s_psel_q[7]}} & user_ip.prdata)" in apb_response
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assert "localparam int NSLV = 8;" in apb_declarations
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assert fabric.count("ribp_if u_") == 1
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assert fabric.count("rib_if u_") == 4
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assert ".mgmt_ribp(u_mgmt_ribp_if)" in bus_fabric
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assert ".user_rib(u_user_rib_if)" in bus_fabric
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assert ".apb_rib(u_apb_rib_if)" in bus_fabric
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assert ".rib(u_rib_if)" in bus_fabric
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assert "`define SOC_IRQ_VECTOR_WIDTH 32" in irq_config
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assert "`define SOC_USER_IRQ_MASK 32'h000E7BFC" in irq_config
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assert "`define SOC_IRQ_RIBP_WIDTH 13" in irq_config
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assert "`define SOC_IRQ_APB_WIDTH 5" in irq_config
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assert "assign irq_o[0] = u_clint_if.software_irq_o[0];" in rib_irq
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assert "assign irq_o[10] = ws2812.irq_o;" in rib_irq
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assert "assign irq_o[11] = gpio.irq_o;" in rib_irq
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assert "assign irq_o[12] = i2c1.irq_o;" in rib_irq
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assert "assign irq_o[0] = pwm.irq_o;" in apb_irq
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assert "assign irq_o[4] = s_rng_irq;" in apb_irq
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assert "s_irq[10]" not in irq_wiring
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assert "s_irq[15]" not in irq_wiring
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assert "s_irq[16] = s_apb_irq[4];" in irq_wiring
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assert "irq_i[10] == 1'b0" in irq_sva
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assert "irq_i[15] == 1'b0" in irq_sva
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assert "irq_i[31] == 1'b0" in irq_sva
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assert "bind retrosoc soc_irq_topology_sva" in irq_sva
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assert filelist.startswith("+incdir+")
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def test_topology_preserves_default_irq_compatibility_mapping() -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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assert document["irq_vector_width"] == 32
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mappings = [
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(
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interrupt["name"],
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interrupt["group"],
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interrupt["group_bit"],
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interrupt["core_bit"],
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interrupt["signal"],
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)
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for interrupt in document["interrupts"]
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]
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assert mappings == [
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("clint_software", "ribp", 0, 0, "u_clint_if.software_irq_o[0]"),
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("clint_timer", "ribp", 1, 1, "u_clint_if.timer_irq_o[0]"),
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("uart0", "ribp", 2, 2, "uart.irq_o"),
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("timer0", "ribp", 3, 3, "s_tim0_irq"),
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("timer1", "ribp", 4, 4, "s_tim1_irq"),
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("psram", "ribp", 5, 5, "psram.irq_o"),
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("spisd", "ribp", 6, 6, "spisd.irq_o"),
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("i2c0", "ribp", 7, 7, "i2c0.irq_o"),
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("i2s", "ribp", 8, 8, "i2s.irq_o"),
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("xpi", "ribp", 9, 9, "xpi.irq_o"),
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("pwm", "apb", 0, 11, "pwm.irq_o"),
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("ps2", "apb", 1, 12, "ps2.irq_o"),
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("rtc", "apb", 2, 13, "u_rtc_if.irq_o"),
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("watchdog_early_warning", "apb", 3, 14, "u_wdg_if.irq_o"),
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("rng", "apb", 4, 16, "s_rng_irq"),
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("ws2812", "ribp", 10, 17, "ws2812.irq_o"),
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("gpio", "ribp", 11, 18, "gpio.irq_o"),
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("i2c1", "ribp", 12, 19, "i2c1.irq_o"),
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]
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def test_topology_always_adds_the_user_apb_target(tmp_path: Path) -> None:
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generate(tmp_path)
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interfaces = (tmp_path / "rtl/soc_apb_interfaces.svh").read_text(encoding="utf-8")
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declarations = (tmp_path / "rtl/soc_apb_declarations.svh").read_text(encoding="utf-8")
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response = (tmp_path / "rtl/soc_apb_response_mux.svh").read_text(encoding="utf-8")
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formal_design = (ROOT / "rtl/mini/formal/rib2apb_formal.sv").read_text(encoding="utf-8")
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formal_properties = (ROOT / "rtl/mini/formal/rib2apb_formal_props.sv").read_text(
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encoding="utf-8"
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)
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assert "apb4_if u_user_ip_apb_if (clk_i, rst_n_i);" in interfaces
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assert "localparam int NSLV = 8;" in declarations
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assert "s_psel_q[7]" in response
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assert "apb4_pure_if user_ip ();" in formal_design
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assert ".user_ip (user_ip)" in formal_design
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assert "logic [ 7:0] psel_comb" in formal_design
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assert "wire [ 7:0] psel_comb" in formal_properties
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def test_topology_rejects_unknown_or_non_rib_regions(tmp_path: Path) -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["ribp_targets"][0]["regions"] = ["UNKNOWN"]
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "unknown region" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["ribp_targets"][0]["regions"] = ["SRAM"]
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "not an active RIBP region" in result.stderr
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def test_topology_rejects_duplicate_region_and_disabled_owner(tmp_path: Path) -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["ribp_targets"][1]["regions"] = ["RIBP_UART0"]
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "multiple targets" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["ribp_targets"][15]["regions"] = ["RIBP_SDIO"]
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "disabled but declares regions" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["fabric_links"][1]["name"] = "mgmt"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "fabric role mgmt is duplicated" in result.stderr
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def test_topology_rejects_invalid_apb_target_ownership(tmp_path: Path) -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["apb_targets"][0]["region"] = "SRAM"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "not an active APB region" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["apb_targets"][7]["slot"] = 0
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "APB target slot 0 is duplicated" in result.stderr
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def test_topology_rejects_invalid_gpio_coverage_and_expression(tmp_path: Path) -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["gpio_alt_functions"][1]["pin"] = 0
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "gpio pin 0 is duplicated" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["gpio_alt_functions"].pop()
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "one entry for every GPIO pin" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["gpio_alt_functions"][0]["alt0"]["do"] = "left + right"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "scalar SystemVerilog reference or constant" in result.stderr
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def test_topology_rejects_invalid_irq_groups_and_bindings(tmp_path: Path) -> None:
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["irq_groups"][1]["name"] = "ribp"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "interrupt group ribp is duplicated" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["interrupts"][1]["group_bit"] = 0
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "interrupt group ribp bit 0 is duplicated" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["interrupts"][1]["core_bit"] = 0
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "core interrupt bit 0 is duplicated" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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rng_index = next(
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index
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for index, interrupt in enumerate(document["interrupts"])
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if interrupt["name"] == "rng"
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)
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document["interrupts"].pop(rng_index)
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "interrupt group apb does not cover every group bit" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["interrupts"][0]["signal"] = "left | right"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "scalar SystemVerilog reference or constant" in result.stderr
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document = json.loads(TOPOLOGY.read_text(encoding="utf-8"))
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document["interrupts"][0]["signal"] = "uart.irq_o"
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result = validate(write_invalid_topology(tmp_path, document))
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assert result.returncode != 0
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assert "core interrupt bit 0 must retain its compatibility binding" in result.stderr
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def test_generated_irq_wiring_preserves_the_expected_core_vector(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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topology_output = tmp_path / "topology"
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generate(topology_output)
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simulation = tmp_path / "soc_irq_topology_tb"
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-I",
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str(topology_output / "rtl"),
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"-s",
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"soc_irq_topology_tb",
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"-o",
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str(simulation),
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str(ROOT / "tests/rtl/soc_irq_topology_tb.sv"),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "SoC topology IRQ routing test passed" in result.stdout
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def test_generated_rib_routes_select_and_return_the_expected_target(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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sv2v = shutil.which("sv2v")
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vvp = shutil.which("vvp")
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if iverilog is None or sv2v is None or vvp is None:
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return
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memory_map_output = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(MEMORY_MAP_GENERATOR),
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"--map",
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str(MEMORY_MAP),
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"--output-dir",
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str(memory_map_output),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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topology_output = tmp_path / "topology"
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generate(topology_output)
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source_list = tmp_path / "ribp_topology.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map_output / 'rtl'}",
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f"+incdir+{topology_output / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "tests/rtl/ribp_topology_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "ribp_topology_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
|
|
simulation = tmp_path / "ribp_topology_tb"
|
|
subprocess.run(
|
|
[
|
|
iverilog,
|
|
"-g2012",
|
|
"-s",
|
|
"ribp_topology_tb",
|
|
"-o",
|
|
str(simulation),
|
|
str(converted),
|
|
],
|
|
check=True,
|
|
)
|
|
result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
|
|
assert "SoC topology RIBP routing test passed" in result.stdout
|