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123 lines
4.0 KiB
Tcl
123 lines
4.0 KiB
Tcl
# Copyright 2025-2026 LibreLane Contributors and retroSoC Authors
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# SPDX-License-Identifier: Apache-2.0
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# Adapted from the IHP SG13G2 LibreLane full-chip template.
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source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
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source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
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set_global_connections
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set secondary_supplies []
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foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
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if {$vdd != $::env(VDD_NET)} {
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lappend secondary_supplies $vdd
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set db_net [[ord::get_db_block] findNet $vdd]
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if {$db_net == "NULL"} {
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set net [odb::dbNet_create [ord::get_db_block] $vdd]
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$net setSpecial
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$net setSigType "POWER"
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}
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}
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if {$gnd != $::env(GND_NET)} {
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lappend secondary_supplies $gnd
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set db_net [[ord::get_db_block] findNet $gnd]
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if {$db_net == "NULL"} {
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set net [odb::dbNet_create [ord::get_db_block] $gnd]
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$net setSpecial
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$net setSigType "GROUND"
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}
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}
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}
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# IHP IO cells carry both core and external-IO power rails on lower-case pins.
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add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern vdd -power
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add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern vss -ground
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add_global_connection -net IOVDD -inst_pattern .* -pin_pattern iovdd -power
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add_global_connection -net IOVSS -inst_pattern .* -pin_pattern iovss -ground
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global_connect -verbose
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set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
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-secondary_power $secondary_supplies
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define_pdn_grid \
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-name stdcell_grid \
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-starts_with POWER \
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-voltage_domain CORE
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(PDN_VERTICAL_LAYER) \
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-width $::env(PDN_VWIDTH) \
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-pitch $::env(PDN_VPITCH) \
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-offset $::env(PDN_VOFFSET) \
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-spacing $::env(PDN_VSPACING) \
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-starts_with POWER
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(PDN_HORIZONTAL_LAYER) \
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-width $::env(PDN_HWIDTH) \
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-pitch $::env(PDN_HPITCH) \
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-offset $::env(PDN_HOFFSET) \
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-spacing $::env(PDN_HSPACING) \
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-starts_with POWER
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add_pdn_connect \
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-grid stdcell_grid \
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-layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
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if {$::env(PDN_ENABLE_RAILS) == 1} {
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(PDN_RAIL_LAYER) \
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-width $::env(PDN_RAIL_WIDTH) \
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-followpins
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add_pdn_connect \
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-grid stdcell_grid \
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-layers "$::env(PDN_RAIL_LAYER) $::env(PDN_VERTICAL_LAYER)"
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}
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if {$::env(PDN_CORE_RING) == 1} {
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add_pdn_ring \
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-grid stdcell_grid \
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-layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)" \
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-widths "$::env(PDN_CORE_RING_VWIDTH) $::env(PDN_CORE_RING_HWIDTH)" \
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-spacings "$::env(PDN_CORE_RING_VSPACING) $::env(PDN_CORE_RING_HSPACING)" \
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-core_offset "$::env(PDN_CORE_RING_VOFFSET) $::env(PDN_CORE_RING_HOFFSET)" \
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-connect_to_pads
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}
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define_pdn_grid \
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-macro \
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-default \
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-name macro_default \
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-starts_with POWER \
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-halo "$::env(PDN_HORIZONTAL_HALO) $::env(PDN_VERTICAL_HALO)"
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add_pdn_connect \
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-grid macro_default \
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-layers "$::env(PDN_VERTICAL_LAYER) $::env(PDN_HORIZONTAL_LAYER)"
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set packet_ram_instances [list \
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u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store.u_packet_ram.u_packet_ram.u_data_high \
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u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store.u_packet_ram.u_packet_ram.u_data_low \
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u_retrosoc.u_apb4_periph.u_apb4_usb2.u_link_domain.u_packet_store.u_packet_ram.u_packet_ram.u_ecc]
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define_pdn_grid \
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-macro \
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-instances $packet_ram_instances \
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-name packet_ram_grid \
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-starts_with POWER
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add_pdn_stripe \
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-grid packet_ram_grid \
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-layer Metal5 \
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-width 2.81 \
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-pitch 11.24 \
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-offset 2.81 \
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-spacing 2.81 \
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-nets "VSS VDD" \
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-starts_with POWER
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add_pdn_connect -grid packet_ram_grid -layers "Metal4 Metal5"
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add_pdn_connect -grid packet_ram_grid -layers "Metal5 TopMetal1"
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