0 Fork 0

mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-05 06:32:37 +00:00

Files

T

maksyuki 3addf412d6 refactor: refactor RTL source paths in style audit and test files

- Added i2c_if.sv and spi_if.sv to rtl_style_audit.json for proper inclusion in style checks.
- Updated test_i2c.py to reference i2c_if.sv from the serial directory instead of the cluster IP directory.
- Modified test_spisd.py to point to spi_if.sv in the storage directory instead of the cluster IP directory.

2026-08-22 19:47:40 +08:00

at24cxxx.sv

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

mic.sv

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

README.md

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

w25q128jvxim.sv

refactor: refactor RTL source paths in style audit and test files

2026-08-22 19:47:40 +08:00

README.md

Device Simulation Models

This directory contains committed device models used only by retroSoC simulation. The models are excluded from the self-owned synthesizable RTL style profile and retain their upstream notices and behavior. The repository import normalizes line endings and trailing whitespace.

File	Upstream source	Revision	Upstream SHA-256
`at24cxxx.sv`	`https://github.com/retroSoC/i2c.git`	`73b024547c5cd70fb8bf801cc7757db2536c604f`	`636ed7e58574735a80943122178da8e1b23a48d443ec11d96ccdbd8618da404b`
`mic.sv`	`https://github.com/retroSoC/i2s.git`	`bd0978e8b45e4cf4c1335a1fa7311385d2a4e805`	`2d5264092bac13f28c5e38cfba4a9288afb6d704c7821f40265177c32715a6b3`
`w25q128jvxim.sv`	`https://github.com/retroSoC/spi.git`	`515cb408806584525605b4747db5e890dbdf1928`	`4b95f007a39854dc2690cf0b608b1b4b56a61adbf1e7c736e7ab5d44d46a112f`