mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
167db9fa86
- Introduced a new overview section detailing the product features and specifications for the retroSoC Mini. - Created a comprehensive peripherals section outlining memory interfaces, GPIO, DMA, timers, multimedia, and encryption components. - Added a pins section that includes pin mapping, GPIO alternate-function matrix, and electrical specifications. - Developed a software section covering boot sequence, runtime environment, applications, and Linux driver status. - Established a style file to define the visual presentation of the datasheet. - Implemented tests for validating datasheet generation and ensuring integrity of engineering inputs.
87 lines
992 B
Plaintext
87 lines
992 B
Plaintext
*.log
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*.hex
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*.elf
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*.o
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*.flash
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*.bin
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*.vvp
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*.vcd
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*.lib
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*.report
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*.ddb
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*.fst
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*.txt
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*.demo
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!requirements/
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!requirements/*.txt
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*.gtkw
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*.vmf
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*.tar.bz2
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*.tbsim
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*.fsdb
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*.conf
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*.rc
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*.aig
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*.so
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*.py[cod]
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__pycache__/
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.vscode
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pic
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video.h
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image.h
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audio_file.h
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.generated_fl
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.sw_build
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.build
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.net_build
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.post_build
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.synth_build
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.vcs_build
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.verilator_build
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.iverilog_build
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.metals
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.mypy_cache
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.pytest_cache
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/build/
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/.cache/
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/dist/
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/configs/local/*.mk
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/configs/local/*.sv
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!/configs/local/*.example.mk
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.vscode
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retrosoc_sections.lds
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retrosoc_syn*
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s110
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icsprout55-pdk
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IHP-Open-PDK
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skywater-pdk
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gf180mcu-pdk
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demo*
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dont_use_cell_*
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nanoV
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tinyQV
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kianV
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hazard3
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def.fl
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*yosys*.fl
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*verilator*.fl
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!rtl/filelist/pdk_ics55_yosys.fl
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!rtl/filelist/pdk_ics55_verilator.fl
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minirv.sv
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user_design
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*.zip
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*.tar*
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ff16
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lvgl-*
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coremark-main
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*wave
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socver.*
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/rtl/managed/clusterip/*
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!/rtl/managed/clusterip/setup.py
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/rtl/managed/mpw/
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/rtl/managed/third_party/
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*result.json
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*.pdf
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/publications/datasheets/assets/
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/publications/media/
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