mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
ed19891bf5
- Introduced Verilator and Yosys warning configurations for ICS55. - Updated RTL filelists to include functional models for ICS55. - Modified memory modules to use wire instead of logic for clock and reset signals. - Enhanced Makefile and Iverilog configurations to support ICS55. - Implemented new simulation cells for ICS55 in the tech library. - Updated regression scripts and tests to include ICS55 support. - Added functionality to prepare ICS55 liberty and simulation models. - Enhanced testbench to validate ICS55 specific components and behaviors.
57 lines
1.4 KiB
Systemverilog
57 lines
1.4 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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interface sdio_if ();
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logic sck_o;
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logic cmd_oe_o;
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logic cmd_di_i;
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logic cmd_do_o;
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logic [3:0] dat_oe_o;
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logic [3:0] dat_di_i;
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logic [3:0] dat_do_o;
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logic irq_o;
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modport dut(
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output sck_o,
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output cmd_oe_o,
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input cmd_di_i,
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output cmd_do_o,
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output dat_oe_o,
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input dat_di_i,
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output dat_do_o,
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output irq_o
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);
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endinterface
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module nmi_sdio (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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nmi_if.slave nmi,
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sdio_if.dut sdio
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// verilog_format: on
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);
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wire dummy0 = clk_i;
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wire dummy1 = rst_n_i;
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// nmi
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assign nmi.rdata = '0;
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assign nmi.ready = '0;
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// sdio
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assign sdio.sck_o = '0;
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assign sdio.cmd_oe_o = '0;
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assign sdio.cmd_do_o = '0;
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assign sdio.dat_oe_o = '0;
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assign sdio.dat_do_o = '0;
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assign sdio.irq_o = '0;
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endmodule
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