mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
ed19891bf5
- Introduced Verilator and Yosys warning configurations for ICS55. - Updated RTL filelists to include functional models for ICS55. - Modified memory modules to use wire instead of logic for clock and reset signals. - Enhanced Makefile and Iverilog configurations to support ICS55. - Implemented new simulation cells for ICS55 in the tech library. - Updated regression scripts and tests to include ICS55 support. - Added functionality to prepare ICS55 liberty and simulation models. - Enhanced testbench to validate ICS55 specific components and behaviors.
22 lines
1.2 KiB
Makefile
22 lines
1.2 KiB
Makefile
# PDK-specific Liberty inputs for the reproducible core-STA baseline.
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ifeq ($(PDK),IHP130)
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OPENSTA_LIBERTY := $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_stdcell/lib/sg13g2_stdcell_slow_1p08V_125C.lib
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OPENSTA_LINK_LIBS := $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_io/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
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ifeq ($(HAVE_SRAM_MACRO),YES)
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OPENSTA_SRAM_LIBS := $(wildcard $(ROOT_PATH)/pdk/IHP-Open-PDK/ihp-sg13g2/libs.ref/sg13g2_sram/lib/*_slow_1p08V_125C.lib)
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endif
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else ifeq ($(PDK),GF180)
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OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/gf180/gf180mcu_fd_sc_mcu7t5v0__ss_125C_4v50.lib
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OPENSTA_LINK_LIBS := $(ROOT_PATH)/.cache/retrosoc/pdk/gf180/gf180mcu_fd_io_retrosoc__ss_125C_4v50.lib
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else ifeq ($(PDK),SKY130)
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OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/sky130/sky130_fd_sc_hd__ss_100C_1v40.lib
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OPENSTA_LINK_LIBS := $(ROOT_PATH)/sta/opensta/sky130_io_blackbox.liberty
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else ifeq ($(PDK),ICS55)
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OPENSTA_LIBERTY := $(ROOT_PATH)/.cache/retrosoc/pdk/ics55/ics55_h7cr_ss.lib
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OPENSTA_LINK_LIBS := $(ROOT_PATH)/pdk/icsprout55-pdk/IP/IO/ICsprout_55LLULP1233_IO_251013/liberty/ICSIOA_N55_3P3_ss_1p08_2p97_125c.lib
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else
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$(error OpenSTA core-STA does not support PDK=$(PDK))
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endif
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OPENSTA_SRAM_LIBS ?=
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